From 3c3850562736e5ef228e05d53de2cea353154a25 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Tue, 7 Nov 2023 13:47:15 +0000 Subject: [PATCH] edits --- test.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test.md b/test.md index 88a2537..659153c 100644 --- a/test.md +++ b/test.md @@ -32,7 +32,7 @@ Specifically this list shows the software needed and the versions used during de After that you can run `make` on the top level directory and it should build everything and start the simulation ### Synthesis and bitstream creation ( for FPGAs ) -Synthesis is based on Yosys. You need to select your board in [common.mk](./common.mk) which is the name of a directory inside inside [system/fpga\_config/](system/fpga_config/) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it. +Synthesis is based on Yosys. You need to set FPGA\_BOARD in [common.mk](./common.mk) to the name of a directory inside [system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it. This list shows the software needed and the versions used during development