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CPU,ASM: Added floating point add and subtract instructions FADD and FSUB

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This commit is contained in:
(Tim) Efthimis Kritikos 2024-02-16 17:48:04 +00:00
parent 19deb0581c
commit 31a26c14ad
3 changed files with 35 additions and 1 deletions
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18
assembly.c
View File

@ -108,6 +108,10 @@
// | 14'hA | Floating point devision | YES | operand | operand | // | 14'hA | Floating point devision | YES | operand | operand |
// +-------+---------------------------------------------+--------------+------------+------------+ // +-------+---------------------------------------------+--------------+------------+------------+
// | 14'hB | Floating point Multiplication | YES | operand 1 | operand 2 | // | 14'hB | Floating point Multiplication | YES | operand 1 | operand 2 |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'hC | Floating point addition | YES | operand 1 | operand 2 |
// +-------+---------------------------------------------+--------------+------------+------------+
// | 14'hD | Floating point subtraction | YES | operand 1 | operand 2 |
// //
// //
// INSTRUCTION FORMAT 2 OPCODE NUM: // INSTRUCTION FORMAT 2 OPCODE NUM:
@ -213,6 +217,12 @@ char *disassemble(uint32_t opcode_be){
case 0x0B: case 0x0B:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"FMUL %%R%0d,%%R%0d",val1,val2); snprintf(ret,MAX_INSTRUCTION_LENGTH,"FMUL %%R%0d,%%R%0d",val1,val2);
break; break;
case 0x0C:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"FADD %%R%0d,%%R%0d",val1,val2);
break;
case 0x0D:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"FSUB %%R%0d,%%R%0d",val1,val2);
break;
default: default:
snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION"); snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
break; break;
@ -413,6 +423,14 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
x=5; x=5;
opcode=0x200B; opcode=0x200B;
params=2; params=2;
}else if(strncmp(line,"FADD ",5)==0){
x=5;
opcode=0x200C;
params=2;
}else if(strncmp(line,"FSUB ",5)==0){
x=5;
opcode=0x200D;
params=2;
}else }else
params=0; params=0;
if(params!=0){ if(params!=0){

14
cpu.c
View File

@ -92,6 +92,8 @@ int decode(struct simdata_t *simdata){
case 0x07: case 0x07:
case 0x0A: case 0x0A:
case 0x0B: case 0x0B:
case 0x0C:
case 0x0D:
simdata->exec_data->in_op1->OP_ADDR=REGISTER; simdata->exec_data->in_op1->OP_ADDR=REGISTER;
simdata->exec_data->in_op2->OP_ADDR=REGISTER; simdata->exec_data->in_op2->OP_ADDR=REGISTER;
break; break;
@ -130,6 +132,8 @@ int decode(struct simdata_t *simdata){
case 0x04: case 0x04:
case 0x0A: case 0x0A:
case 0x0B: case 0x0B:
case 0x0C:
case 0x0D:
simdata->exec_data->out_op->OP_ADDR=REGISTER; simdata->exec_data->out_op->OP_ADDR=REGISTER;
simdata->exec_data->out_op->data=op2; simdata->exec_data->out_op->data=op2;
break; break;
@ -163,6 +167,8 @@ int decode(struct simdata_t *simdata){
break; break;
case 0x0A: simdata->exec_data->ALU_OP=ALU_FDIV; break; case 0x0A: simdata->exec_data->ALU_OP=ALU_FDIV; break;
case 0x0B: simdata->exec_data->ALU_OP=ALU_FMUL; break; case 0x0B: simdata->exec_data->ALU_OP=ALU_FMUL; break;
case 0x0C: simdata->exec_data->ALU_OP=ALU_FADD; break;
case 0x0D: simdata->exec_data->ALU_OP=ALU_FSUB; break;
default: default:
return 1; return 1;
} }
@ -298,6 +304,14 @@ int exec(struct simdata_t *simdata){
*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])* *(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])*
*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data]); *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data]);
break; break;
case ALU_FADD:
*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data])+
*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]);
break;
case ALU_FSUB:
*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data])-
*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]);
break;
default: default:
return 1; return 1;
} }

4
cpu.h
View File

@ -32,7 +32,9 @@ enum ALU_OP_t {
ALU_SR, ALU_SR,
ALU_CMP, ALU_CMP,
ALU_FDIV, ALU_FDIV,
ALU_FMUL ALU_FMUL,
ALU_FADD,
ALU_FSUB
}; };
enum OP_ADDR_t { enum OP_ADDR_t {