From 31a26c14adadf8962e3d0cb44fc0c8112446526e Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Fri, 16 Feb 2024 17:48:04 +0000
Subject: [PATCH] CPU,ASM: Added floating point add and subtract instructions
 FADD and FSUB

---
 assembly.c | 18 ++++++++++++++++++
 cpu.c      | 14 ++++++++++++++
 cpu.h      |  4 +++-
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/assembly.c b/assembly.c
index 483a03c..b398dfc 100644
--- a/assembly.c
+++ b/assembly.c
@@ -108,6 +108,10 @@
 //  | 14'hA | Floating point devision                     |      YES     |   operand  |  operand   |
 //  +-------+---------------------------------------------+--------------+------------+------------+
 //  | 14'hB | Floating point Multiplication               |      YES     |  operand 1 |  operand 2 |
+//  +-------+---------------------------------------------+--------------+------------+------------+
+//  | 14'hC | Floating point addition                     |      YES     |  operand 1 |  operand 2 |
+//  +-------+---------------------------------------------+--------------+------------+------------+
+//  | 14'hD | Floating point subtraction                  |      YES     |  operand 1 |  operand 2 |
 //
 //
 //  INSTRUCTION FORMAT 2 OPCODE NUM:
@@ -213,6 +217,12 @@ char *disassemble(uint32_t opcode_be){
 			case 0x0B:
 				snprintf(ret,MAX_INSTRUCTION_LENGTH,"FMUL %%R%0d,%%R%0d",val1,val2);
 				break;
+			case 0x0C:
+				snprintf(ret,MAX_INSTRUCTION_LENGTH,"FADD %%R%0d,%%R%0d",val1,val2);
+				break;
+			case 0x0D:
+				snprintf(ret,MAX_INSTRUCTION_LENGTH,"FSUB %%R%0d,%%R%0d",val1,val2);
+				break;
 			default:
 				snprintf(ret,MAX_INSTRUCTION_LENGTH,"UNRECOGNISED INSTRUCTION");
 				break;
@@ -413,6 +423,14 @@ int64_t assemble_line(char *line, struct assembler_context_t *assembler_context)
 			x=5;
 			opcode=0x200B;
 			params=2;
+		}else if(strncmp(line,"FADD ",5)==0){
+			x=5;
+			opcode=0x200C;
+			params=2;
+		}else if(strncmp(line,"FSUB ",5)==0){
+			x=5;
+			opcode=0x200D;
+			params=2;
 		}else
 			params=0;
 		if(params!=0){
diff --git a/cpu.c b/cpu.c
index cf6f90f..a61965c 100644
--- a/cpu.c
+++ b/cpu.c
@@ -92,6 +92,8 @@ int decode(struct simdata_t *simdata){
 				case 0x07:
 				case 0x0A:
 				case 0x0B:
+				case 0x0C:
+				case 0x0D:
 					simdata->exec_data->in_op1->OP_ADDR=REGISTER;
 					simdata->exec_data->in_op2->OP_ADDR=REGISTER;
 					break;
@@ -130,6 +132,8 @@ int decode(struct simdata_t *simdata){
 				case 0x04:
 				case 0x0A:
 				case 0x0B:
+				case 0x0C:
+				case 0x0D:
 					simdata->exec_data->out_op->OP_ADDR=REGISTER;
 					simdata->exec_data->out_op->data=op2;
 					break;
@@ -163,6 +167,8 @@ int decode(struct simdata_t *simdata){
 					break;
 				case 0x0A: simdata->exec_data->ALU_OP=ALU_FDIV;  break;
 				case 0x0B: simdata->exec_data->ALU_OP=ALU_FMUL;  break;
+				case 0x0C: simdata->exec_data->ALU_OP=ALU_FADD;  break;
+				case 0x0D: simdata->exec_data->ALU_OP=ALU_FSUB;  break;
 				default:
 					return 1;
 			}
@@ -298,6 +304,14 @@ int exec(struct simdata_t *simdata){
 						*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data])*
 							*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data]);
 						break;
+					case ALU_FADD:
+						*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data])+
+							*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]);
+						break;
+					case ALU_FSUB:
+						*(float*)&result = *(float*)(&simdata->registers->GPR[simdata->exec_data->in_op2->data])-
+							*(float*)(&simdata->registers->GPR[simdata->exec_data->in_op1->data]);
+						break;
 					default:
 						return 1;
 				}
diff --git a/cpu.h b/cpu.h
index c10b79f..e4e96cc 100644
--- a/cpu.h
+++ b/cpu.h
@@ -32,7 +32,9 @@ enum ALU_OP_t {
 	ALU_SR,
 	ALU_CMP,
 	ALU_FDIV,
-	ALU_FMUL
+	ALU_FMUL,
+	ALU_FADD,
+	ALU_FSUB
 };
 
 enum OP_ADDR_t {