(Tim) Efthymios Kritikos 9b350ec117 Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore		2023-01-24 20:27:15 +00:00
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Makefile	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00
multiplexer-tb.v	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00
multiplexer.v	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00