24 lines
438 B
Verilog
24 lines
438 B
Verilog
module test;
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/* Make a reset that pulses once. */
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reg reset = 0;
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initial begin
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# 17 reset = 1;
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# 11 reset = 0;
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# 29 reset = 1;
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# 11 reset = 0;
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# 100 $stop;
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end
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/* Make a regular pulsing clock. */
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reg clk = 0;
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always #5 clk = !clk;
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wire [7:0] value;
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counter c1 (value, clk, reset);
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initial
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$monitor("At time %t, value = %h (%0d)",
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$time, value, value);
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endmodule // test
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