Efthimis/COMS30046_2022_TB-2_playground
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base: Efthimis:a13ffe57b6ff44c928b006cb1bba45ce40fcced8
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compare: Efthimis:b749a5610e26611cacbe369c99b0ad87023599d2
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No commits in common. "a13ffe57b6ff44c928b006cb1bba45ce40fcced8" and "b749a5610e26611cacbe369c99b0ad87023599d2" have entirely different histories.
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6 changed files with 1 additions and 137 deletions
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2
.gitignore vendored
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@ -1,4 +1,2 @@
*.vvp *.vvp
*.vpi
*.lx2
*.o *.o

2
verilog_iverilog/VPI_example/Makefile
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@ -12,4 +12,4 @@ simulate: ${OBJECTS}
iverilog $^ -o $@ iverilog $^ -o $@
clean: clean:
rm ${OBJECTS} hello.vpi -f rm ${OBJECTS} -f

18
verilog_iverilog/clock/Makefile
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@ -1,18 +0,0 @@
SOURCES=clock.v clock-tb.v
VPP=clock.vpp
.PHONY: run
run: ${VPP}
vvp ${VPP}
.PHONY: wave
wave: ${VPP}
vvp ${VPP} -lxt2
gtkwave test.lx2 gtkwave_savefile.gtkw
${VPP} : ${SOURCES}
iverilog -g2012 $^ -o $@
.PHONY: clean
clean:
rm -f ${VPP} test.lx2

28
verilog_iverilog/clock/clock-tb.v
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@ -1,28 +0,0 @@
module tb;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
reg enable;
reg [7:0] delay;
clock_gen u0(enable, clk1);
clock_gen #(.FREQ(100000)) u1(enable, clk2);
clock_gen #(.FREQ(200000)) u2(enable, clk3);
clock_gen #(.FREQ(400000)) u3(enable, clk4);
integer i ;
initial begin
$dumpfile("test.lx2");
$dumpvars(0,u1,u2,u3);
enable <= 0;
for ( i = 0; i < 10; i=i+1) begin
delay = $random;
#(delay) enable <= ~enable;
$display("i=%0d delay=%0d", i, delay);
#50;
end
#50 $finish;
end
endmodule

61
verilog_iverilog/clock/clock.v
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@ -1,61 +0,0 @@
`timescale 1ns/1ps
module clock_gen (input enable, output reg clk);
parameter FREQ = 1000; // in HZ
parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage
real clk_pd = 1.0/FREQ * 1000000; // convert to ns
real clk_on = DUTY/100.0 * clk_pd;
real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
real quarter = clk_pd/4;
real start_dly = quarter * PHASE/90;
reg start_clk;
initial begin
$display("FREQ = %0d kHz", FREQ);
$display("PHASE = %0d deg", PHASE);
$display("DUTY = %0d %%", DUTY);
$display("PERIOD = %0.1f ms", clk_pd);
$display("CLK_ON = %0.1f ms", clk_on);
$display("CLK_OFF = %0.1f ms", clk_off);
$display("QUARTER = %0.1f ms", quarter);
$display("START_DLY = %0.1f ms", start_dly);
end
// Initialize variables to zero
initial begin
clk <= 0;
start_clk <= 0;
end
// When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
if (enable) begin
#(start_dly) start_clk = 1;
end else begin
#(start_dly) start_clk = 0;
end
end
// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
if (start_clk) begin
clk = 1;
while (start_clk) begin
#(clk_on) clk = 0;
#(clk_off) clk = 1;
end
clk = 0;
end
end
endmodule

27
verilog_iverilog/clock/gtkwave_savefile.gtkw
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@ -1,27 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Tue Feb 7 17:50:40 2023
[*]
[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/playground/verilog_iverilog/clock/test.lx2"
[dumpfile_mtime] "Tue Feb 7 17:49:38 2023"
[dumpfile_size] 4777
[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/playground/verilog_iverilog/clock/gtkwave_savefile.gtkw"
[timestart] 0
[size] 1342 1059
[pos] -1 -1
*-17.808613 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[sst_width] 221
[signals_width] 102
[sst_expanded] 1
[sst_vpaned_height] 313
@28
tb.u1.clk[0]
tb.u1.enable[0]
tb.u2.clk[0]
tb.u2.enable[0]
tb.u3.clk[0]
@29
tb.u3.enable[0]
[pattern_trace] 1
[pattern_trace] 0