COMS30046_2022_TB-2_playground/verilog_iverilog/multiplexer/Makefile

SOURCES=multiplexer.v multiplexer-tb.v
VVP=multiplexer.vvp

run: ${VVP}
	vvp ${VVP}

${VVP} : ${SOURCES}
	iverilog $^ -o $@

clean:
	rm -f ${VVP}
Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore 2023-01-24 20:27:15 +00:00			`SOURCES=multiplexer.v multiplexer-tb.v`
Didn't add all files on last commit 2023-02-07 17:58:07 +00:00			`VVP=multiplexer.vvp`
Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore 2023-01-24 20:27:15 +00:00
Didn't add all files on last commit 2023-02-07 17:58:07 +00:00			`run: ${VVP}`
			`vvp ${VVP}`
Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore 2023-01-24 20:27:15 +00:00
Didn't add all files on last commit 2023-02-07 17:58:07 +00:00			`${VVP} : ${SOURCES}`
Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore 2023-01-24 20:27:15 +00:00			`iverilog $^ -o $@`

			`clean:`
Didn't add all files on last commit 2023-02-07 17:58:07 +00:00			`rm -f ${VVP}`