(Tim) Efthimis Kritikos fd31eb704c Made the simulation stop at an unrecognised instruction or other error		2023-02-11 01:05:19 +00:00
..
alu.v	Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions!	2023-02-09 20:17:15 +00:00
boot_code.asm	Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing	2023-02-10 18:21:19 +00:00
gtkwave_savefile.gtkw	Improved execution state logic, cleaned up code and fixed register file output enable	2023-02-10 01:45:27 +00:00
Makefile	Removed now useless register init code and changed disas command name	2023-02-10 15:41:38 +00:00
memory.v	Hadn't added all files to previous commit	2023-02-10 13:26:23 +00:00
proc_state_def.v	Added unaligned access for instructions and data and fixed register file access	2023-02-10 12:02:20 +00:00
processor.v	Made the simulation stop at an unrecognised instruction or other error	2023-02-11 01:05:19 +00:00
registers.v	Removed now useless register init code and changed disas command name	2023-02-10 15:41:38 +00:00
testbench.v	Made the simulation stop at an unrecognised instruction or other error	2023-02-11 01:05:19 +00:00