56 lines
1.7 KiB
Verilog
56 lines
1.7 KiB
Verilog
/* config.v - Configuration values for the 9086 CPU and the system around it
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/** Runtime Verbosity **/
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//`define DEBUG_REG_WRITES
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//`define DEBUG_PC_ADDRESS
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//`define DEBUG_DATA_READ_WRITES
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/** OUTPUT **/
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/* These are usually set at build time*/
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//`define CALCULATE_IPC
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//`define OTUPUT_JSON_STATISTICS
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/** Optimisations **/
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/* Enables the ability to check if an instruction in the input
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* buffer is completed and mark it ready instead of always waiting
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* for the maximum instruction size worth of bytes */
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`define EARLY_VALID_INSTRUCTION
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/* Size is in powers of two with minimal 3.
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* 3 : 8 Bytes
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* 4 : 16 Bytes
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* 5 : 32 Bytes
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* . : ... */
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`define L1_CACHE_SIZE 4 // Don't change it! some parts of code still assume it to be 4
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/********** Internal **********/
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`ifdef EARLY_VALID_INSTRUCTION
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`define EARLY_VALID_INSTRUCTION_ 1
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`else
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`define EARLY_VALID_INSTRUCTION_ 0
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`endif
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`ifdef OTUPUT_JSON_STATISTICS
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`define CALCULATE_IPC
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`endif
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