86 lines
3.6 KiB
Plaintext
86 lines
3.6 KiB
Plaintext
/* ucode.txt - The contents of the microcode rom for the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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//wbo: Wbit overwrite, {VALUE,ENABLE}. ex 11 would force one, 10 wouldn't do anything
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//
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//krs: Keep registers, selects weather the register port 1 and/or 2
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// addresses is set on that microcoded instruction or kept as it
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// was before allowing for registers to be parameterised.
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// {Register_write_port,Register_port2, Register_port1}
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//
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//rr2: reg_read_port2_addr
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//
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//imd: IN_MOD
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//
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//rr1: reg_read_port1_addr
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//
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//a1f: ALU 1 operation (function)
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// 000:ALU_OP_ADD
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// 001:ALU_OP_SUB
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// 010:ALU_OP_AND
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// 011:ALU_OP_OR
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// 100:ALU_OP_XOR
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// 101:ALU_OP_ADD_SIGNED_B
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// 110:ALU_OP_SUB_REVERSE
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//
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//a1o: OUT_MOD. Handled in `PROC_EX_STATE_EXIT
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//
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//a12: In ALU 1 sel 2
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//
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//a11: In ALU 1 sel 1
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//
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//rwa: Register Write Address
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//
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//nxs: Next State
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// 00: PROC_EX_STATE_ENTRY
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// 01: PROC_DE_LOAD_16_PARAM
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// 10: PROC_DE_LOAD_8_PARAM
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// 11: PROC_MEMIO_READ
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//
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//Nxt M: Next microcode address
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@000 0000_000_000__00__00_0000__00_000000
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// 36 34 32 28 25 21 18 15 13 11 7 5 0
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// CALL
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@001 _00_000_0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
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@002 _00_000_0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
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@003 _00_000_0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
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// RET
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@004 _00_000_0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
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@005 _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
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// STOS
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@006 _00_000_1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
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@007 _11_000_zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI
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// PUSH
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@008 _00_010_0000_011_1100_001_011__00__01_1100__00_001001 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
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@009 _00_010_0000_011_zzzz_000_110__01__11_zzzz__00_000000 // ALU_1: 0 ALU_2: REG ALU_OP:ADD ALU_out: [SP]
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// POP
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@00a _00_100_0000_110_zzzz_011_011__00__11_zzzz__11_001011 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: REG
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@00b _00_000_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
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