87 lines
2.5 KiB
Verilog
87 lines
2.5 KiB
Verilog
/* config.v - Configuration values for the 9086 CPU and the system around it
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/** Runtime Verbosity **/
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//`define DEBUG_REG_WRITES
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//`define DEBUG_PC_ADDRESS
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//`define DEBUG_DATA_READ_WRITES
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/** OUTPUT **/
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/* These are usually set at build time*/
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//`define CALCULATE_IPC
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//`define OUTPUT_JSON_STATISTICS
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/** Optimisations **/
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/* Enables the ability to check if an instruction in the input
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* buffer is completed and mark it ready instead of always waiting
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* for the maximum instruction size worth of bytes */
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`define EARLY_VALID_INSTRUCTION
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/*********** CURRENTLY DOESN'T WORK *************/
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/* Enables the ability in BIU to pre-decode two instructions, one after the other in memory*/
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//`define DOUBLE_INSTRUCTION_LOAD
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/************************************************/
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/* Size is in powers of two with minimal 3.
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* 3 : 8 Bytes
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* 4 : 16 Bytes
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* 5 : 32 Bytes
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* . : ... */
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`define L1_CACHE_SIZE 4
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//// These are usually set at build time
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//
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// /* This is the "virtual" synthesised ram, so for example on an FPGA
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// * This would be made inside the fabric of the fpga. */
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// `define BUILTIN_RAM 512
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// ////// ATTENTION: PLEASE IF BUILTIN_RAM DOESN'T COVER THE ENTIRE (CURRENTLY)
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// // 16 BIT RANGE, I.E. ISN'T 32768, PLEASE SET THE FOLLOWING FLAG
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// `define NOT_FULL
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/********** Internal **********/
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`ifdef SYNTHESIS
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`undef DEBUG_REG_WRITES
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`undef DEBUG_PC_ADDRESS
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`undef DEBUG_DATA_READ_WRITES
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`undef CALCULATE_IPC
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`undef OUTPUT_JSON_STATISTICS
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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`define CALCULATE_IPC
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`endif
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`ifdef DOUBLE_INSTRUCTION_LOAD
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/*Needed for DOUBLE_INSTRUCTION_LOAD*/
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`define EARLY_VALID_INSTRUCTION
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`endif
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`ifdef EARLY_VALID_INSTRUCTION
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`define INCLUDE_EARLY_CALC_CIRCUIT
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`define EARLY_VALID_INSTRUCTION_ 1
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`else
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`define EARLY_VALID_INSTRUCTION_ 0
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`endif
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`ifdef CALCULATE_IPC
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`define INCLUDE_EARLY_CALC_CIRCUIT
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`endif
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