301 lines
9.5 KiB
Verilog
301 lines
9.5 KiB
Verilog
/* processor.v - implementation of most functions of the 9086 processor
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "exec_state_def.v"
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`include "alu_header.v"
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`include "config.v"
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`include "ucode_header.v"
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`include "error_header.v"
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`define PROC_STATE_BITS 3
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`define PROC_RESET 3'b000
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`define PROC_DE_STATE_ENTRY 3'b001
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`define PROC_HALT 3'b011
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//HALT: active high
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//IOMEM: 1=IO 0=MEM
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//BHE: active low
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//write: active low
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//read: active low
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//reset: active low
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module processor (
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/* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR
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/* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,output reg new_instruction
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`endif
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`ifdef OTUPUT_JSON_STATISTICS
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/* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
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`endif
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);
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`ifdef OTUPUT_JSON_STATISTICS
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assign jump_req_debug=biu_jump_req;
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`endif
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/* If there is an error either from the decoder or execution unit set it to ERROR */
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assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;
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reg [`PROC_STATE_BITS-1:0] proc_state;
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/*############ Execution Unit ################################################### */
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wire [1:0] in_alu_sel1, in_alu_sel2;
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assign in_alu_sel1 = DE_OUTPUT_sampled[44:43];
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assign in_alu_sel2 = DE_OUTPUT_sampled[46:45];
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wire [`EXEC_STATE_BITS-1:0] exec_state;
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reg valid_exec_data, set_initial_values;
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wire [`ERROR_BITS-1:0] EXEC_ERROR;
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wire use_exec_reg_addr;
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wire [3:0] EXEC_reg_read_port1_addr;
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wire [15:0] ALU_O;
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wire [7:0]EXEC_FLAGS;
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wire [15:0] PARAM1_INIT, PARAM2_INIT;
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assign PARAM1_INIT = DE_OUTPUT_sampled[23:8];
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assign PARAM2_INIT = DE_OUTPUT_sampled[39:24];
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wire [2:0] IN_MOD,OUT_MOD;
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assign IN_MOD=DE_OUTPUT_sampled[2:0];
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assign OUT_MOD=DE_OUTPUT_sampled[49:47];
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wire [`ALU_OP_BITS-1:0] ALU_OP;
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assign ALU_OP = DE_OUTPUT_sampled[42:40];
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wire next_exec;
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execute_unit execute_unit (
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/* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
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/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
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/* */ ,set_initial_values,next_exec
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/* PARAM */ ,PARAM1_INIT,PARAM2_INIT
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/* STATE CONTROL */ ,exec_state, next_state
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
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/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
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/* FLAGS */ ,EXEC_FLAGS
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/* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
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);
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/*############ Bus Interface Unit ############################################### */
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wire [15:0] INSTRUCTION_LOCATION, BIU_ADDRESS_INPUT;
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wire [15:0] BIU_DATA;
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wire [31:0] INSTRUCTION;
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wire biu_write_request, biu_read_request, BIU_VALID_DATA;
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wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION;
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reg valid_instruction_ack;
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BIU BIU(
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/* Outside world */ clock,reset,external_address_bus
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/* */ ,external_data_bus,read,write,BHE,IOMEM
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/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
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/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
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/* */ ,valid_instruction_ack
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`ifdef OTUPUT_JSON_STATISTICS
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/* Statistics */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
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`endif
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);
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assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
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/*############ Decoder ########################################################## */
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wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
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reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
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reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
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wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT;
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reg [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT_sampled;
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wire DE_DEPENDS_ON_PREVIOUS;
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decoder decoder(
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/* INPUT */ INSTRUCTION[31:16],FLAGS,
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/* MICROCODE */ ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr,
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/* OUTPUT */ DE_OUTPUT,DE_DEPENDS_ON_PREVIOUS
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);
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wire [2:0] RM;
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assign RM = DE_OUTPUT_sampled[5:3];
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wire memio_address_select;
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assign memio_address_select=DE_OUTPUT_sampled[6:6];
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wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr;
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assign DE_reg_read_port1_addr=DE_OUTPUT_sampled[53:50];
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assign DE_reg_read_port2_addr=DE_OUTPUT_sampled[57:54];
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wire [3:0] reg_write_addr;
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assign reg_write_addr=DE_OUTPUT_sampled[61:58];
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wire MEM_OR_IO;
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assign MEM_OR_IO = DE_OUTPUT_sampled[7:7];
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wire Wbit, Sbit, opcode_size;
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assign opcode_size=DE_OUTPUT_sampled[62:62];
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assign Sbit=DE_OUTPUT_sampled[63:63];
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assign Wbit=DE_OUTPUT_sampled[64:64];
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wire [`ERROR_BITS-1:0] DE_ERROR;
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assign HALT = DE_OUTPUT_sampled[65:65];
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assign DE_ERROR = DE_OUTPUT_sampled[`ERROR_BITS+65:66];
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wire [`EXEC_STATE_BITS-1:0] next_state;
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assign next_state=DE_OUTPUT_sampled[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66];
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/*############ Registers ######################################################## */
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reg [15:0] FLAGS;
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reg [15:0] ProgCount;
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wire [3:0] reg_read_port1_addr;
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assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr;
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wire [15:0] reg_read_port1_data, reg_read_port2_data;
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wire reg_write_we;
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register_file register_file(
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/* WRITE */ .write_port1_addr(reg_write_addr),
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/* */ .write_port1_data(ALU_O),
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/* */ .write_port1_we(reg_write_we),
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/* READ 1 */ .read_port1_addr(reg_read_port1_addr),
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/* */ .read_port1_data(reg_read_port1_data),
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/* READ 2 */ .read_port2_addr(DE_reg_read_port2_addr),
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/* */ .read_port2_data(reg_read_port2_data)
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);
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/*############ Processor State Machine ########################################## */
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/*** RESET LOGIC ***/
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always @(negedge reset) begin
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proc_state <= `PROC_HALT; //TODO: race condition ??
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`ifdef CALCULATE_IPC
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new_instruction<=0;
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`endif
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end
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always @(posedge reset) begin
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proc_state <= `PROC_RESET;
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/* need early init */
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valid_instruction_ack <= 0;
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instant_response <= 0;
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stalled_response <= 0;
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end
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/*** Processor stages ***/
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wire [2:0] instr_end;
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InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},instr_end);
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reg [23:0] INSTRUCTION_BUFFER;
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reg owe_set_init;
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//TODO: Why do we need to make a local copy on a register for the code inside the always @(next_state) to read it?
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// For some reason the raw VALID_INSTRUCTION signal reads always 1 and it has something to do with the block
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// being triggered by next_exec
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reg VALID_INSTRUCTION_lc;
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always @(VALID_INSTRUCTION)begin VALID_INSTRUCTION_lc<=VALID_INSTRUCTION; end
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reg instant_response, stalled_response;
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reg wait_exec;
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always @(next_exec) begin
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proc_state<=`PROC_DE_STATE_ENTRY;
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if ( VALID_INSTRUCTION_lc == 1 && DE_DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION) begin
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instant_response <= !instant_response;
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end else begin
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wait_exec<=0;
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end
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end
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always @(instant_response or stalled_response) begin
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DE_OUTPUT_sampled <= DE_OUTPUT;
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if(SIMPLE_MICRO==0||owe_set_init==1)begin
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/* This runs at the start of the execution of an 8086 instruction */
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`ifdef DEBUG_PC_ADDRESS
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$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
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`endif
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`ifdef CALCULATE_IPC
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new_instruction <= !new_instruction;
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`endif
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valid_instruction_ack <= !valid_instruction_ack;
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owe_set_init<=0;
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set_initial_values<= !set_initial_values;
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ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
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INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
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end
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/* switch to microcode decoding */
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
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end else begin
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/* This runs at the start of each execution cycle, with microcode this is more than once per 8086 instruction */
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valid_exec_data<=!valid_exec_data;
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if( SIMPLE_MICRO == 1 ) begin
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ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
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if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
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/*Finished microcode*/
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SIMPLE_MICRO <= 0;
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end
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end
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wait_exec<=1;
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end
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end
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always @(posedge clock) begin
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case(proc_state)
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`PROC_RESET:begin
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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DE_OUTPUT_sampled <= 0;
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SIMPLE_MICRO <= 0;
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proc_state <= `PROC_DE_STATE_ENTRY;
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owe_set_init <= 0;
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set_initial_values<=0;
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wait_exec<=0;
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valid_exec_data<=0;
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end
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`PROC_DE_STATE_ENTRY:begin
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if ( ( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) && wait_exec==0) begin
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stalled_response <= !stalled_response;
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end
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end
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`PROC_HALT:begin
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end
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default:begin
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end
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endcase
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end
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always @(exec_state) begin
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if(exec_state == `EXEC_WAIT)
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FLAGS <= {8'b0,EXEC_FLAGS}; //TODO: don't set all of them all the time!
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end
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endmodule
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