130 lines
2.7 KiB
Verilog
130 lines
2.7 KiB
Verilog
/* testbench.v - Testbench for the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/*In hz */
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`define CPU_SPEED 1000
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module tb;
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wire clock;
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reg reset;
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reg clk_enable;
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wire [19:0]address_bus;
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wire [15:0]data_bus_write;
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wire rd,wr,HALT;
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wire [2:0] ERROR;
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wire IOMEM;
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system system( .clock(clock),
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.reset(reset),
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.address_bus(address_bus),
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.data_bus_write(data_bus_write),
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.rd(rd),
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.wr(wr),
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.HALT(HALT),
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.ERROR(ERROR),
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.IOMEM(IOMEM)
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);
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clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
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string memdump_name;
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initial begin
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clk_enable = 1;
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do_reset = 0;
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end
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reg [2:0]do_reset;
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always @(posedge clock) begin
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case(do_reset)
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3'd0:begin
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do_reset<=1;
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end
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3'd1:begin
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do_reset<=2;
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reset <= 0;
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end
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3'd2:begin
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do_reset<=3;
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reset <= 0;
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end
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3'd3:begin
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do_reset<=4;
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reset <= 1;
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end
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3'd4:begin
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end
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endcase
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end
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endmodule
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/*Clock generator*/
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module clock_gen (input enable, output reg clk);
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parameter FREQ = 1000; // in HZ
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parameter PHASE = 0; // in degrees
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parameter DUTY = 50; // in percentage
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real clk_pd = 1.0/FREQ * 1000000000; // convert to ms
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real clk_on = DUTY/100.0 * clk_pd;
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real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
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real quarter = clk_pd/4;
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real start_dly = quarter * PHASE/90;
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reg start_clk;
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initial begin
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end
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// Initialise variables to zero
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initial begin
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clk = 0;
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start_clk = 0;
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end
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// When clock is enabled, delay driving the clock to one in order
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// to achieve the phase effect. start_dly is configured to the
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// correct delay for the configured phase. When enable is 0,
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// allow enough time to complete the current clock period
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always @ (posedge enable or negedge enable) begin
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if (enable) begin
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#(start_dly) start_clk = 1;
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end else begin
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#(start_dly) start_clk = 0;
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end
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end
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// Achieve duty cycle by a skewed clock on/off time and let this
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// run as long as the clocks are turned on.
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always @(posedge start_clk) begin
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if (start_clk) begin
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clk = 1;
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while (start_clk) begin
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#(clk_on) clk = 0;
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#(clk_off) clk = 1;
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end
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clk = 0;
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end
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end
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endmodule
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