(Tim) Efthimis Kritikos
1966ab78b4
I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
40 lines
1.4 KiB
Makefile
40 lines
1.4 KiB
Makefile
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#### ECP5 specific ####
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ECP5_DEVICE=25F
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# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
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# 85F: Create bitstream for the LFE5U-85F
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ECP5_PACKAGE=CSFBGA285
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# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
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FPGA_FILE_EXT=dfu
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#This is on the 8th postiion in the chip id, for example
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# LFE5U-25-7BG381I
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# ^---------- this would be a 7 speed grade
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#
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# 6 is the slowest and 8 is the fastest
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ECP5_SPEED_GRADE=8
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ROM_PART_ID=24lc512
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######## End of user configuration ########
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#NOT USED OUTSIDE OF HERE
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FPGA_SOC_COMMON_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v peripherals/I2C_driver_multiplexer.v peripherals/CPU_to_I2C_driver_bridge.v
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FPGA_SOC_SOURCES=${FPGA_SOC_COMMON_SOURCES} external_ip/litedram_core_ecp5_phy.v
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FPGA_SOC_SIM_SOURCES=${FPGA_SOC_COMMON_SOURCES} fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt external_ip/litedram_core_ecp5_phy_sim.v
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FPGA_BOOTCODE=../boot_code/i2c_bootloader.stxt
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ROM_FILE=../boot_code/brainfuck_mandelbrot.bin
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upload_bitstream: dfu_upload
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upload_bootrom: minipro_upload
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${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr-ecp5_${BUILD_NAME}.bit
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${Q}cp "$^" "$@"
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${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json:${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json
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${Q}cp "$^" "$@"
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