128 lines
3.9 KiB
Verilog
128 lines
3.9 KiB
Verilog
/* Wishbone_driver.v - Implements a classic wishbone master
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module Wishbone_IO_driver (
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input wire clock,
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input wire reset_n,
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input wire [2:0] address,
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input wire [15:0] data_bus_in,
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output reg [15:0] data_bus_out,
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input read_n,
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input write_n,
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input chip_select_n,
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input wire wb_ctrl_ack,
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output wire [29:0] wb_ctrl_adr,
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output wire [1:0] wb_ctrl_bte,
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output wire [2:0] wb_ctrl_cti,
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output wire wb_ctrl_cyc,
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input wire [31:0] wb_ctrl_dat_r,
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output wire [31:0] wb_ctrl_dat_w,
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input wire wb_ctrl_err,
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output wire [3:0] wb_ctrl_sel,
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output wire wb_ctrl_stb,
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output wire wb_ctrl_we
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);
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reg [13:0]WISHBONE_ADDR=14'd0;
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reg WISHBONE_ACTIVE_CYCLE=1'b0;
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wire WISHBONE_ERROR_IN;
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reg [3:0]WISHBONE_SELECT=4'd0;
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reg WISHBONE_VALID_TRANSFER=1'b0;
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reg WISHBONE_WRITE=1'b1;
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wire WISHBONE_ACK_IN;
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reg [31:0]WISHBONE_DATA_READ=32'd0;
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wire [31:0]WISHBONE_DATA_WRITE;
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assign WISHBONE_ACK_IN=wb_ctrl_ack;
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assign wb_ctrl_adr={16'd0,WISHBONE_ADDR};
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assign WISHBONE_ERROR_IN=wb_ctrl_err;
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assign wb_ctrl_sel=WISHBONE_SELECT;
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assign wb_ctrl_stb=WISHBONE_VALID_TRANSFER;
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assign wb_ctrl_cyc=WISHBONE_ACTIVE_CYCLE;
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assign wb_ctrl_we=WISHBONE_WRITE;
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assign wb_ctrl_bte=2'b00; // Burst Type Extension 00:Linear burst
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assign wb_ctrl_cti=3'b000; // Cycle Type Idenfier 000:Classic cycle
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assign WISHBONE_DATA_WRITE=wb_ctrl_dat_r;
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assign wb_ctrl_dat_w=WISHBONE_DATA_READ;
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reg [31:0]WISHBONE_READ_BUFFER;
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reg [1:0]just_transacted;
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reg [1:0]WISHBONE_STATUS;
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wire CYCLE_END=(WISHBONE_ACK_IN==1'b1);//||WISHBONE_ERROR_IN==1'b1);
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always @( posedge clock )begin
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if(reset_n==0)begin
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just_transacted<=2'b0;
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end
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if(just_transacted==2'd1&&CYCLE_END==1'b1)begin
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WISHBONE_READ_BUFFER<=WISHBONE_DATA_WRITE;
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end
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if(chip_select_n==0 && write_n==0 )begin
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case (address)
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3'h0: WISHBONE_DATA_READ[15:0] <=data_bus_in;
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3'h1: WISHBONE_DATA_READ[31:16]<=data_bus_in;
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3'h2: WISHBONE_ADDR[13:0]<=data_bus_in[13:0];
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3'h3: begin end
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default: begin end
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endcase
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case (address)
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3'h3: begin
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WISHBONE_ACTIVE_CYCLE<=1;
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WISHBONE_VALID_TRANSFER<=1;
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WISHBONE_SELECT<=4'hF;
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end
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default: begin end
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endcase
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if(address==3'h3)begin
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WISHBONE_WRITE<=1'b1;//data_bus_in[0:0];
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if(data_bus_in[0:0]==1'b1)begin //write req
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just_transacted<=2'd2;
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end else begin
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just_transacted<=2'd1;
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end
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end
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end else if(just_transacted!=2'd0&&CYCLE_END==1'b1)begin // In the unlikely scenario that the CPU wants to write without having checked for the previous write
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WISHBONE_STATUS[0:0]<=WISHBONE_ACK_IN;
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WISHBONE_STATUS[1:1]<=WISHBONE_ERROR_IN;
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WISHBONE_ACTIVE_CYCLE<=0;
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WISHBONE_VALID_TRANSFER<=0;
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just_transacted<=2'b0;
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end
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if ( chip_select_n==0 && read_n==0 )begin
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case (address)
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/* verilator lint_off BLKSEQ */
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/* Makes icarus verilog work as expected, not too sure if it helps real hardware yet*/
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3'h0: data_bus_out = WISHBONE_READ_BUFFER[15:0];
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3'h1: data_bus_out = WISHBONE_READ_BUFFER[31:16];
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3'h2: data_bus_out = {13'd0,WISHBONE_STATUS,just_transacted==2'd0||CYCLE_END==1'b1}; //1:NOT BUSY 0:BUSY
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default: data_bus_out = 16'h0;
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/* verilator lint_on BLKSEQ */
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endcase
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end
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end
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endmodule
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