59 lines
2.1 KiB
Verilog
59 lines
2.1 KiB
Verilog
/* alu.v - implementation of the ALU of the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "alu_header.v"
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module ALU(input [15:0]A,input [15:0]B,output reg [15:0]OUT,input [`ALU_OP_BITS-1:0]op,output wire [7:0]FLAGS,input Wbit);
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reg C_FLAG;
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wire signed [15:0]SIGNED_B;
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wire signed [7:0]SIGNED_8B;
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assign SIGNED_B=B;
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assign SIGNED_8B=B[7:0];
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assign FLAGS={(Wbit==1)?OUT[15:15]:OUT[7:7],(Wbit==1) ? (OUT[15:0]=='h0000) : (OUT[7:0]=='h00),5'b0,C_FLAG};
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always @ ( * ) begin
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if(Wbit==1)begin
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case (op)
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`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
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`ALU_OP_ADD_SIGNED_B: {C_FLAG,OUT}=A+SIGNED_B;
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`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
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`ALU_OP_SUB_REVERSE: {C_FLAG,OUT}=B-A;
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`ALU_OP_AND: begin C_FLAG=0;OUT=A&B; end
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`ALU_OP_OR: begin C_FLAG=0;OUT=A|B; end
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`ALU_OP_XOR: begin C_FLAG=0;OUT=A^B; end
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`ALU_OP_SHIFT_LEFT: begin C_FLAG=(A&16'h8000)==16'h8000;OUT=A<<B; end
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endcase
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end else begin
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OUT[15:8]=8'b0;
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case (op)
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`ALU_OP_ADD: {C_FLAG,OUT[7:0]}=A[7:0]+B[7:0];
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`ALU_OP_ADD_SIGNED_B: {C_FLAG,OUT[7:0]}=A[7:0]+SIGNED_8B;
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`ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0];
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`ALU_OP_SUB_REVERSE: {C_FLAG,OUT[7:0]}=B[7:0]-A[7:0];
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`ALU_OP_AND: begin C_FLAG=0;OUT[7:0]=A[7:0]&B[7:0]; end
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`ALU_OP_OR: begin C_FLAG=0;OUT[7:0]=A[7:0]|B[7:0]; end
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`ALU_OP_XOR: begin C_FLAG=0;OUT[7:0]=A[7:0]^B[7:0]; end
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`ALU_OP_SHIFT_LEFT: begin C_FLAG=(A&16'h80)==16'h80;OUT[7:0]=A[7:0]<<B; end
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endcase
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end
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end
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endmodule
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