10 lines
206 B
Verilog
10 lines
206 B
Verilog
module ADDER16(input [15:0]A,input [15:0]B, input oe,output [15:0]OUT, output carry);
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wire c;
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wire [15:0]sum;
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assign {c,sum} = A+B;
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assign OUT = !oe ? sum : 16'hz;
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assign carry = !oe ? c : 'hz;
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endmodule
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