74 lines
2.1 KiB
Verilog
74 lines
2.1 KiB
Verilog
/* Wishbone_driver.v - Implements a classic wishbone master that maps directly in memory space
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module Wishbone_memory_driver (
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input wire clock,
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/* verilator lint_off UNUSEDSIGNAL */
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input wire reset_n,
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/* verilator lint_on UNUSEDSIGNAL */
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input wire [19:0] address,
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input wire [15:0] data_bus_in,
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output reg [15:0] data_bus_out,
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output wire wait_state,
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input read_n,
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input write_n,
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input chip_select_n,
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input BHE,
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input wire wb_mem_ack,
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output wire [24:0] wb_mem_adr,
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output reg wb_mem_cyc,
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/* verilator lint_off UNUSEDSIGNAL */
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// I don't yet use the upper word
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input wire [31:0] wb_mem_data_r,
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/* verilator lint_on UNUSEDSIGNAL */
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output wire [31:0] wb_mem_data_w,
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/* verilator lint_off UNUSEDSIGNAL */
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input wire wb_mem_err,
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/* verilator lint_on UNUSEDSIGNAL */
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output wire [3:0] wb_mem_sel,
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output reg wb_mem_stb,
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output wire wb_mem_we
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);
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assign wb_mem_adr={6'd0,address[19:1]};
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assign wb_mem_sel={2'b11,!BHE,!address[0]};
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always @(posedge clock)begin
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wb_mem_cyc<=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n);
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wb_mem_stb<=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n);
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end
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always @(posedge wb_mem_ack)begin
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data_bus_out<=wb_mem_data_r[15:0];
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end
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assign wb_mem_data_w={16'd0,data_bus_in};
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assign wait_state=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n);
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assign wb_mem_we=read_n;
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endmodule
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