32 lines
1.0 KiB
Verilog
32 lines
1.0 KiB
Verilog
/* general.v - Pieces of code that can be used by multiple other modules
|
|
|
|
This file is part of the 9086 project.
|
|
|
|
Copyright (c) 2023 Efthymios Kritikos
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
|
|
|
module mux4 (in1,in2,in3,in4, sel,out);
|
|
input [1:0] sel;
|
|
parameter WIDTH=16;
|
|
input [WIDTH-1:0] in1,in2,in3,in4;
|
|
output [WIDTH-1:0] out;
|
|
|
|
assign out = (sel == 'b00) ? in1 :
|
|
(sel == 'b01) ? in2 :
|
|
(sel == 'b10) ? in3 :
|
|
in4;
|
|
|
|
endmodule
|