(Tim) Efthimis Kritikos 533f346f9b Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.		2023-12-07 16:39:04 +00:00
..
config.mk	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00
fpga_top.v	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00
pin_constraint.pcf	Added OrangeCrab board-specific code to connect the cpu to the outside world	2023-11-02 20:40:04 +00:00
testbench.cpp	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00
verilator_config.vlt	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00