396 lines
5.7 KiB
NASM
396 lines
5.7 KiB
NASM
.org 0xF800
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mov sp,#STACK
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mov bx,#initdram_txt
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call print
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WAIT_PLL:
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inw #0x20
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test al,#0x04
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jz WAIT_PLL
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;;; DO ALL INIT STUFF ;;;
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;////sdram_software_control_on///
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MOV BX,#0x0000
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MOV AX,#0x000E
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call sdram_dfii_control_write
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;/////////////////////////////////
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MOV BX,#0x0000
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MOV AX,#0x0000
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CALL ddrctrl_init_done_write
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mov bx,#0x0000
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mov ax,#0x0000
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call ddrctrl_init_error_write
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mov bx,#0x0000
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mov ax,#0x000C
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY11:
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MOV AX,#0xF000
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DELAY1:
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INC AX
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JNZ DELAY1
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INC DL
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JNZ DELAY11
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000E
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY21:
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MOV AX,#0xF000
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DELAY2:
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INC AX
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JNZ DELAY2
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INC DL
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JNZ DELAY21
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MOV BX,#0x0000
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MOV AX,#0x0200
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0002
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0003
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0006
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0001
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0320
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV DL,#0xF0
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DELAY31:
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MOV AX,#0xF000
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DELAY3:
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INC AX
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JNZ DELAY3
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INC DL
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JNZ DELAY31
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MOV BX,#0x0000
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MOV AX,#0x0400
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x0003
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call command_p0
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;////sdram_software_control_off///
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MOV BX,#0x0000
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MOV AX,#0x0001
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call sdram_dfii_control_write
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;////////////////////////////////
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;Signify end of init
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MOV BX,#0x0000
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MOV AX,#0x0001
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CALL ddrctrl_init_done_write
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;;;;;;;;;; PROBABLY NOT NECESSARY
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MOV DL,#0xF0
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DELAY41:
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MOV AX,#0xF000
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DELAY4:
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INC AX
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JNZ DELAY4
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INC DL
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JNZ DELAY41
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;;; CHECK ;;;
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inw #0x20
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test al,#0x01
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jz failram
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mov bx,#OK_txt
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call print
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JMP FINISHED_DDR
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failram:
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mov bx,#FAIL_txt
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call print
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mov bx,#NOT_RDY_txt
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call print
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inw #0x20
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test al,#0x02
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jz skip_err
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mov bx,#ERR_ASRT_txt
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call print
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skip_err:
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inw #0x20
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test al,#0x04
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jnz skip_pll
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mov bx,#PLL_ERR_txt
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call print
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skip_pll:
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hlt
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FINISHED_DDR:
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MOV DI,#0x2000
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MOV AX,#0xAAAA
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV AX,#0x6666
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MOV AX,[DI]
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CMP AX,#0xAAAA
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JNZ FAILED
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MOV BX,#MEMTEST_PASS
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CALL print
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MOV AL,#0x48
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x3000
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MOV AL,#0x65
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x4000
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MOV AL,#0x6c
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x5000
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MOV AL,#0x6c
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x6000
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MOV AL,#0x6f
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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HLT
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FAILED:
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MOV BX,#MEMTEST_FAIL
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CALL print
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MOV DL,#0xF0
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DELAY51:
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MOV AX,#0x5000
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DELAY5:
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INC AX
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JNZ DELAY5
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INC DL
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JNZ DELAY51
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MOV DI,#0x2000
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MOV AX,#0xAAAA
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV AX,#0x0000
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MOV AX,[DI]
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CMP AL,#0xAA
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JNZ FAILED2
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MOV BX,#MEMTEST_PASS
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CALL print
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HLT
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FAILED2:
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MOV BX,#MEMTEST_FAIL
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CALL print
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MOV AX,[DI]
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CMP AL,#0xAA
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JNZ FAILED3
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MOV BX,#MEMTEST_PASS
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CALL print
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HLT
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FAILED3:
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MOV BX,#MEMTEST_FAIL
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CALL print
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HLT
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;;; HELPER FUNCTION
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command_p0:
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call WISHBONE_SET_DATA
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MOV AX,#0x0401 ;ORIG=0x1804L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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MOV AX,#0x0001
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MOV BX,#0x0000
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call WISHBONE_SET_DATA
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MOV AX,#0x0402 ;ORIG=0x1808L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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#AX: Lower 16 bits data
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#BX: Upper 16 bits data
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sdram_dfii_pi0_address_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0403 ;ORIG=0x180cL
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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sdram_dfii_pi0_baddress_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0404 ;ORIG=0x1810L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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sdram_dfii_control_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0400 ;ORIG=0x1800L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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ddrctrl_init_done_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0000 ;ORIG=0x0L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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ddrctrl_init_error_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0001 ;ORIG=0x4L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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;
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DO_WRITE_TRANSACTION:
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mov ax,#0x01
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outw #0x46
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mov bl,#0x01
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WB_WRITE_LOOP:
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inc bl
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jz WB_WRITE_TIMEOUT
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inw #0x44
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test al,#0x01
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jz WB_WRITE_LOOP
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test al,#0x04
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jnz WB_WRITE_ERR
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ret
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WB_WRITE_TIMEOUT:
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mov bx,#WISHBONE_TIMEOUT_txt
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call print
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hlt
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WB_WRITE_ERR:
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mov bx,#WISHBONE_ERROR_txt
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call print
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hlt
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#AX: address
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WISHBONE_SET_ADDRESS:
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outw #0x44
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ret
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#AX: Lower 16bits
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#BX: Upper 16bits
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WISHBONE_SET_DATA:
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outw #0x40
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MOV AX,BX
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outw #0x42
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ret
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print:
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mov al,[bx]
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cmp al,#0
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je print_exit
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out byte #0xA5
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inc bx
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jmp print
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print_exit:
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ret
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initdram_txt: .ASCII 'Init LiteDram: \0'
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OK_txt: .ASCII 'OK\n\0'
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PLL_ERR_txt: .ASCII 'PLL_ERR \0' ; PLL_ERR: pll_lock is not asserted
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ERR_ASRT_txt: .ASCII 'ERR_ASRT \0' ; ERR_ASRT: init_error is asserted
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NOT_RDY_txt: .ASCII 'NOT_RDY \0' ; NOT READY: init_done is not asserted
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FAIL_txt: .ASCII 'FAIL\n\0'
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WISHBONE_TIMEOUT_txt: .ASCII 'FAIL\nWISHBONE TIMEOUT\0'
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WISHBONE_ERROR_txt: .ASCII 'FAIL\nWISHBONE ERROR\0'
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MEMTEST_PASS: .ASCII 'MEMTEST PASSED\n\0'
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MEMTEST_FAIL: .ASCII 'MEMTEST FAILED\n\0'
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.BLKB 18 ; Using the text as stack space for the compiled program
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STACK: ; brainfuck_mandelbrot depends on stack being at the end
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.ORG 0xFFF0
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MOV AX,#0xF800
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JMP AX
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.ORG 0xFFFF
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DB 0x00 ;Make sure a full 64KiB image
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