106 lines
2.1 KiB
Verilog
106 lines
2.1 KiB
Verilog
`timescale 1ns/1ps
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module tb;
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wire clock;
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reg reset;
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reg clk_enable;
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wire [19:0]address_bus;
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wire [15:0]data_bus;
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wire rd,wr,romcs,HALT;
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wire ERROR;
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processor p(clock,reset,address_bus,data_bus,rd,wr,HALT,ERROR);
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rom bootrom(address_bus,data_bus,rd,romcs);
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`define CPU_SPEED 1000
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clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
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assign romcs=0;
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integer cycles=0;
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initial begin
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$dumpfile("test.lx2");
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$dumpvars(0,p);
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reset = 0;
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clk_enable <= 1;
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#($random%500)
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#(`CPU_SPEED)
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reset = 1;
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end
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always @(posedge HALT) begin
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$display("Processor halted.\nCycles run for: %d",cycles);
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$writememh("memdump.txt", bootrom.memory);
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#(`CPU_SPEED) //Just for the waveform
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$finish;
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end
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always @(posedge ERROR) begin
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$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
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$writememh("memdump.txt", bootrom.memory);
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#(`CPU_SPEED) //Just for the waveform
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$finish;
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end
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always @(posedge clock)begin
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if(reset==1)
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cycles=cycles+1;
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end
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endmodule
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/*Clock generator*/
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module clock_gen (input enable, output reg clk);
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parameter FREQ = 1000; // in HZ
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parameter PHASE = 0; // in degrees
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parameter DUTY = 50; // in percentage
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real clk_pd = 1.0/FREQ * 1000000; // convert to ms
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real clk_on = DUTY/100.0 * clk_pd;
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real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
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real quarter = clk_pd/4;
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real start_dly = quarter * PHASE/90;
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reg start_clk;
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initial begin
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end
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// Initialize variables to zero
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initial begin
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clk <= 0;
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start_clk <= 0;
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end
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// When clock is enabled, delay driving the clock to one in order
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// to achieve the phase effect. start_dly is configured to the
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// correct delay for the configured phase. When enable is 0,
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// allow enough time to complete the current clock period
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always @ (posedge enable or negedge enable) begin
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if (enable) begin
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#(start_dly) start_clk = 1;
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end else begin
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#(start_dly) start_clk = 0;
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end
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end
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// Achieve duty cycle by a skewed clock on/off time and let this
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// run as long as the clocks are turned on.
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always @(posedge start_clk) begin
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if (start_clk) begin
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clk = 1;
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while (start_clk) begin
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#(clk_on) clk = 0;
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#(clk_off) clk = 1;
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end
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clk = 0;
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end
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end
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endmodule
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