106 lines
2.7 KiB
Verilog
106 lines
2.7 KiB
Verilog
/* system.v - A basic test system with memory and IO for the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`timescale 1ns/1ps
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`include "error_header.v"
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module system ( input clock,input reset, output [19:0]address_bus, inout [15:0]data_bus,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
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processor p(clock,reset,address_bus,data_bus,rd,wr,BHE,IOMEM,HALT,ERROR);
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doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM);
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string waveform_name;
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initial begin
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p);
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end
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end
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//integer killswitch=0;
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//always @(posedge clock) begin
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// killswitch <= killswitch +1;
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// if( killswitch == 20000 )begin
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// if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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// $writememh(memdump_name, system.sysmem.memory,0,32767);
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// end
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// $finish;
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// end
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//end
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )
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$write("%s" ,data_bus[15:8]);
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end
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reg [1:0] finish;
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string memdump_name;
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always @(posedge HALT) begin
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$display("Processor halted.\nCycles run for: %d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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always @(posedge clock) begin
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/* Allow some clock cycles for the waveform*/
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case(finish)
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2'd0: begin end
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2'd1: finish <= 2;
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2'd2: finish <= 3;
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2'd3: $finish;
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endcase
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end
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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end
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endcase
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$display("Cycles run for: %d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, system.sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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end
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integer cycles=0;
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always @(posedge clock)begin
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if(reset==1)
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cycles<=cycles+1;
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else
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cycles<=0;
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end
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endmodule
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