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fpga_config/OrangeCrab_r0.2.1
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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alu_header.v
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Added partial support for the software interrupt INT instruction
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2023-03-08 07:26:28 +00:00 |
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alu.v
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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biu.v
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did some cleanup relating to the generation of the VALID_INSTRUCTION signal
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2023-11-01 05:00:09 +00:00 |
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boot_code.asm
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Improved DOS char print code
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2023-03-14 07:20:30 +00:00 |
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config.v
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Made the size of the cache variable
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2023-05-18 11:21:27 +01:00 |
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decoder.v
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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error_header.v
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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exec_state_def.v
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General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode
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2023-05-29 02:29:15 +01:00 |
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execute.v
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Lots of cleanup mainly on processor.v
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2023-06-01 02:13:55 +01:00 |
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general.v
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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Makefile
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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memory.v
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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processor.v
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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registers.v
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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system.v
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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testbench.cpp
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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testbench.v
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Changed slogan and cleaned up some small pieces of code
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2023-05-23 16:18:33 +01:00 |
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ucode_header.v
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Added partial support for the software interrupt INT instruction
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2023-03-08 07:26:28 +00:00 |
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ucode.txt
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Changed slogan and cleaned up some small pieces of code
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2023-05-23 16:18:33 +01:00 |
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verilator_makefile
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Removed erroneous file and run aspell
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2023-03-21 14:51:39 +00:00 |
