75 lines
2.3 KiB
Verilog
75 lines
2.3 KiB
Verilog
/* memory.v - implementation of memory external to the 9086 CPU for testing purposes
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This warning is because we don't use the full address bus. */
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/* verilator lint_off UNUSEDSIGNAL */
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module doublemem
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#(
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parameter RAM_SIZE_IN_BYTES,
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parameter ADDRESS_WIDTH=$clog2(RAM_SIZE_IN_BYTES)
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)
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( input [ ADDRESS_WIDTH-1 : 0 ] address,
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output [15:0] cpu_read_data,
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input [15:0] cpu_write_data,
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input rd,
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input wr,
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input BHE,
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input cs,
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input clock
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);
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/* verilator lint_on UNUSEDSIGNAL */
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reg [15:0] memory [0:(RAM_SIZE_IN_BYTES/2)-1];
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initial begin
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`ifndef YOSYS
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string boot_code;
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if(!$value$plusargs("BOOT_CODE=%s",boot_code))begin
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$display("No boot code specified. Please add +BOOT_CODE=<path> to your vvp args");
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$finish;
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end
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$readmemh(boot_code, memory,0,(RAM_SIZE_IN_BYTES/2)-1);
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`else
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//TODO: don't have it hard coded
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$readmemh("../boot_code/bios.stxt", memory,0,(RAM_SIZE_IN_BYTES/2)-1); // 2KiB
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`endif
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end
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`ifdef USE_HIGH_IMPEDANCE
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assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][15:8] : `16'hz;
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assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[ADDRESS_WIDTH-1:1]][ 7:0] : `16'hz;
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`else
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assign cpu_read_data[7:0] = memory[address[ADDRESS_WIDTH-1:1]][15:8];
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assign cpu_read_data[15:8] = memory[address[ADDRESS_WIDTH-1:1]][ 7:0];
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`endif
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always @(posedge clock) begin
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if( cs == 0 && wr == 0) begin
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if(BHE==0)
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memory[address[ADDRESS_WIDTH-1:1]][7:0]<=cpu_write_data[15:8];
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if(address[0]==0)
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memory[address[ADDRESS_WIDTH-1:1]][15:8]<=cpu_write_data[7:0];
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end
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end
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endmodule
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