366 lines
9.8 KiB
Verilog
366 lines
9.8 KiB
Verilog
/* execute.v - Implements the instruction execution logic
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module execute_unit (
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/* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input
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/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/
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/* */ ,input set_initial_values, output reg work
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/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT
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/* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state
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/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
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/* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we
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/* FLAFS */ ,output reg [7:0] FLAGS
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/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req
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);
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assign _exec_state_ = exec_state;
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assign _ALU_O_ = ALU_O;
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reg [`EXEC_STATE_BITS-1:0] exec_state;
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reg [15:0] PARAM1,PARAM2;
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/*############ ALU / Execution units ################################################## */
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mux4 #(.WIDTH(16)) MUX16_1A(
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/*0*/ PARAM1,
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/*1*/ reg_read_port1_data,
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/*2*/ ProgCount[15:0],
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/*3*/ 16'd0, /*0 Constant*/
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in_alu_sel1,
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ALU_A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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/*0*/ PARAM2,
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/*1*/ reg_read_port2_data,
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/*2*/ ProgCount[15:0],
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/*3*/ 16'd0, /*0 Constant*/
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in_alu_sel2,
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ALU_B);
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wire [15:0] ALU_A;
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wire [15:0] ALU_B;
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wire [15:0] ALU_O;
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wire [7:0] ALU_FLAGS;
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ALU ALU1(
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/* INPUT 1 */ .A(ALU_A),
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/* INPUT 2 */ .B(ALU_B),
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/* OUTPUT */ .OUT(ALU_O),
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/* OPERATION */ .op(ALU_OP),
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/* FLAGS */ .FLAGS(ALU_FLAGS),
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/* Wbit */ .Wbit(Wbit)
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);
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/*############ Execute logic ########################################################## */
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always @(posedge valid_input) begin
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if(work == 0)begin
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exec_state <= init_state;
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work <= 1;
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reg_write_we <= 1;
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biu_jump_req <= 0;
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use_exec_reg_addr <= 0;
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end
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end
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always @( set_initial_values) begin
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PARAM1 <= PARAM1_INIT;
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PARAM2 <= PARAM2_INIT;
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end
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always @(negedge reset) begin
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exec_state <= `EXEC_HALT;
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end
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always @(posedge reset) begin
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exec_state <= `EXEC_RESET;
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end
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`define unimpl_addressing_mode exec_state <= `EXEC_DONE;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
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always @(posedge clock) begin
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case (exec_state)
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`EXEC_RESET: begin
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work <= 0;
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biu_write_request <= 0;
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biu_read_request <= 0;
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biu_data_direction <= 0;
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biu_jump_req <= 0;
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reg_write_we <= 1;
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exec_state <= `EXEC_DONE;
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ERROR <= `ERR_NO_ERROR;
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end
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`EXEC_DONE:begin
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reg_write_we <= 1;
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use_exec_reg_addr <= 0;
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if(valid_input)begin
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exec_state <= init_state;
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work <= 1;
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end else
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work <= 0;
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end
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`EXEC_DE_LOAD_REG_TO_PARAM:begin
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work <= 1;
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PARAM2<=reg_read_port2_data;
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case(IN_MOD)
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3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
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default: exec_state <= `EXEC_WRITE_ENTRY;
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endcase
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end
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`EXEC_DE_LOAD_8_PARAM:begin
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work <= 1;
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if(opcode_size==0)begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 <= {{8{INSTRUCTION_BUFFER[23:23]}},INSTRUCTION_BUFFER[23:16]};
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end else begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
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default: exec_state <= `EXEC_WRITE_ENTRY;
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endcase
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end else begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 <= {{8{INSTRUCTION_BUFFER[15:15]}},INSTRUCTION_BUFFER[15:8]};
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end else begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
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end
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
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default: exec_state <= `EXEC_WRITE_ENTRY;
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endcase
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end
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`EXEC_DE_LOAD_16_PARAM:begin
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work <= 1;
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if(opcode_size==0)begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
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PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8];
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end else begin
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PARAM1[15:8] <= INSTRUCTION_BUFFER[7:0];
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PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
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default: exec_state <= `EXEC_WRITE_ENTRY;
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endcase
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end
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`EXEC_MEMIO_READ:begin
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work <= 1;
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/*Decode MOD R/M, read the data and place it to PARAM1*/
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case (IN_MOD)
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3'b000,
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3'b001,
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3'b010:begin
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case (RM)
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3'b000:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`unimpl_addressing_mode
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr <= 4'b1110;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_READ_SETADDR;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr <= 4'b1111;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_READ_SETADDR;
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end
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3'b110:begin
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/*d16 */
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`unimpl_addressing_mode
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr <= 4'b1011;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_READ_SETADDR;
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end
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endcase
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if(IN_MOD!=3'b000)begin
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/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
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`unimpl_addressing_mode;
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end
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end
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3'b110:begin /* SP Indirect read*/
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reg_read_port1_addr <= 4'b1100;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_READ_SETADDR;
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end
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default:begin
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`unimpl_addressing_mode
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end
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endcase
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end
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`EXEC_MEMIO_READ_SETADDR:begin
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work <= 1;
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if(memio_address_select==0)
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BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
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else
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BIU_ADDRESS_INPUT <= ALU_O;
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if ( BIU_VALID_DATA == 1 ) begin
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exec_state <= `EXEC_WRITE_ENTRY;
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PARAM2 <= BIU_DATA;
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biu_read_request <= 0;
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biu_data_direction <= 0;
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end else begin
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biu_data_direction <= 1;
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biu_read_request <= 1;
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end
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end
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`EXEC_NEXT_INSTRUCTION:begin
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work <= 0;
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/*necessary for biu to see we went on another state from decode to give us a new instruction*/
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exec_state <= `EXEC_DONE;
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end
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`EXEC_WRITE_ENTRY:begin
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FLAGS[7:0] <= ALU_FLAGS[7:0];
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case(OUT_MOD)
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3'b000,
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3'b001,
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3'b010 : begin
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if(memio_address_select==1)
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exec_state <= `EXEC_MEMIO_WRITE;
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else
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case (RM) /* Duplicate code with write... */
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3'b000:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`unimpl_addressing_mode
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr <= 4'b1110;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_WRITE;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr <= 4'b1111;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_WRITE;
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end
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3'b110:begin
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/*d16 */
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`unimpl_addressing_mode
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr <= 4'b1011;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_WRITE;
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end
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endcase
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work <= 1;
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end
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3'b011:begin
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reg_write_we <= 0;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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3'b100:begin /*No output*/
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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3'b101:begin /* Program Counter*/
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BIU_ADDRESS_INPUT <= ALU_O[15:0];
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biu_jump_req <= 1;
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exec_state <= `EXEC_JUMP_RELEASE;
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work <= 1;
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end
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3'b110:begin /* SP Indirect write*/
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reg_read_port1_addr <= 4'b1100;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_WRITE;
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work <= 1;
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end
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3'b111:begin /* Write to PRAM1 (for microcode calculations) */
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PARAM1 <= ALU_O;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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default:begin
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`unimpl_addressing_mode
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work <= 1;
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end
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endcase
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end
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`EXEC_JUMP_RELEASE:begin
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biu_jump_req <= 0;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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`EXEC_MEMIO_WRITE:begin
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/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
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/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
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biu_write_request <= 1;
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if(memio_address_select==0)
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BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
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else
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BIU_ADDRESS_INPUT <= ALU_O;
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if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
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biu_write_request <= 0;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end else
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work <= 1;
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end
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`EXEC_HALT:begin
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end
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default:begin
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end
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endcase
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end
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`undef unimpl_addressing_mode
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endmodule
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