399 lines
13 KiB
Verilog
399 lines
13 KiB
Verilog
/* biu.v - implementation of the 9086 bus interface unit. The logic that
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controls all external bus functions
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "config.v"
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`define BIU_HALT 4'b0000
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`define BIU_NEXT_ACTION 4'b0001
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`define BIU_READ 4'b0010
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`define BIU_RESET 4'b0011
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`define BIU_PUT_BYTE 4'b0100
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`define BIU_PUT_UNALIGNED_16BIT_DATA 4'b0101
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`define BIU_PUT_ALIGNED_16BIT_DATA 4'b0110
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`define BIU_PUT_UNALIGNED_PREP_NEXT2 4'b1000
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`define BIU_WRITE_EXIT 4'b1001
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`define BIU_WRITE_RELEASE 4'b1010
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`define BIU_GET_ALIGNED_DATA 4'b1011
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`define BIU_GET_UNALIGNED_DATA 4'b1100
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`define BIU_GET_SECOND_BYTE 4'b1101
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`define BIU_GET_SECOND_BYTE1 4'b1110
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module BIU (
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/***************** GENERAL *****************/
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/* */ input clock, input reset
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/**************** OUTSIDE WORLD ****************/
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/* */ ,output wire [19:0] external_address_bus
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/* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM
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/**************** OUTPUT TO DE ****************/
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/* */ ,output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION
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/* */ ,output reg VALID_DATA, output reg DATA_DIR
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/**************** INPUT FROM DE ****************/
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,input Wbit, input MEM_OR_IO, input valid_instruction_ack
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/**************** INPUT FROM EX ****************/
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/* */ ,input jump_req, input write_request, input read_request
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/* */ ,input[15:0] ADDRESS_INPUT
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/************ BIDIRECTIONAL WITH EX ************/
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/* */ ,inout [15:0] DATA
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`ifdef OTUPUT_JSON_STATISTICS
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/***************** STATISTICS *****************/
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/* */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
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`endif
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);
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`ifdef OTUPUT_JSON_STATISTICS
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assign FIFO_SIZE_STAT = FIFO_SIZE;
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assign VALID_INSTRUCTION_STAT = ((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_) || ((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_) || ((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_) || (FIFO_SIZE>3);
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`endif
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reg [15:0] data_bus_output_register;
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assign external_data_bus=read?data_bus_output_register:16'hz;
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reg [15:0] DATA_OUT;
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assign DATA=DATA_DIR ? 16'hz:DATA_OUT;
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`define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE))
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reg [7:0] INPUT_FIFO [`FIFO_SIZE_BYTES-1:0];
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reg [`L1_CACHE_SIZE-1:0] FIFO_start; /*inclusive*/
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reg [`L1_CACHE_SIZE-1:0] FIFO_end; /*exclusive*/
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wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE = FIFO_end-FIFO_start;
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reg [3:0] biu_state;
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always @(negedge reset) begin
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biu_state <= `BIU_HALT;
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write <= 1;
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end
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always @(posedge reset) begin
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biu_state <= `BIU_RESET;
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/* verilator lint_off BLKSEQ */
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FIFO_start = `L1_CACHE_SIZE'b0;
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FIFO_end = `L1_CACHE_SIZE'b0;
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/* verilator lint_on BLKSEQ */
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end
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reg jump_req_latch;
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reg func;
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reg [19:0]INSTRUCTION_ADDRESS;
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reg [19:0]DATA_ADDRESS;
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assign external_address_bus= func ? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
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always @(posedge clock) begin
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if ( jump_req_latch ) begin
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/* verilator lint_off BLKSEQ */
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FIFO_start = 0;
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FIFO_end = 0;
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
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INSTRUCTION_LOCATION <= ADDRESS_INPUT;
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func <= 1;
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jump_req_latch <= 0;
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if (biu_state==`BIU_READ)
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biu_state <= `BIU_NEXT_ACTION;
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end else begin
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case(biu_state)
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`BIU_HALT: begin
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end
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`BIU_NEXT_ACTION: begin /* decide if we can read, if we are full or if we need to do something else */
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if (write_request) begin
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func<=0;
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DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
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DATA_DIR <= 1 ;
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IOMEM <= MEM_OR_IO;
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biu_state <= (Wbit==0) ? `BIU_PUT_BYTE : (ADDRESS_INPUT[0:0]?`BIU_PUT_UNALIGNED_16BIT_DATA:`BIU_PUT_ALIGNED_16BIT_DATA) ;
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INSTRUCTION_ADDRESS <= {4'b0,INSTRUCTION_LOCATION} ;
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/* verilator lint_off BLKSEQ */
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FIFO_end=FIFO_start;
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/* verilator lint_on BLKSEQ */
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end else if ( read_request ) begin
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func<=0;
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DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
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DATA_DIR <= 0;
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IOMEM <= MEM_OR_IO;
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read <= 0;
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BHE <= 0;
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biu_state <= (ADDRESS_INPUT[0:0])?`BIU_GET_UNALIGNED_DATA:`BIU_GET_ALIGNED_DATA;
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end else begin
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if ( FIFO_SIZE!={`L1_CACHE_SIZE{1'b1}} ) begin
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func<=1;
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biu_state <= `BIU_READ;
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write <= 1;
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read <= 0;
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IOMEM <= 0;
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BHE <= 0;
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end else begin
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biu_state <= `BIU_NEXT_ACTION;
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end
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end
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`ifdef EARLY_VALID_INSTRUCTION
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if(FIFO_start==FIFO_end) begin
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/*TODO: I would use FIFO_SIZE==0 here or better yet add an else at the
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end but since FIFO_start and FIFO_end are updated in a blocking
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manner it seems that the assign statement updating FIFO_SIZE
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doesn't work. PLEASE CLEAN UP THIS MESS */
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VALID_INSTRUCTION <= 0;
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end else if((Isit1==1) && (FIFO_SIZE!=0))begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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end else if((fifoIsize==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1))begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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end else if((fifoIsize==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2))begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
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end else if(FIFO_SIZE > `L1_CACHE_SIZE'd3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
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end
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`else
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if(FIFO_start==FIFO_end) begin
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/*TODO: Same as on the first statment on the other side of the `ifdef */
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VALID_INSTRUCTION <= 0;
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end else if(FIFO_SIZE>`L1_CACHE_SIZE'd3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
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end
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`endif
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end
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/*************** INSTRUCTION FIFO READ ***************/
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`BIU_READ: begin
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if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<{{(`L1_CACHE_SIZE-1){1'b1}},1'b0})begin
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INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
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INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] <= external_data_bus[15:8];
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/* verilator lint_off BLKSEQ */
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FIFO_end = FIFO_end+`L1_CACHE_SIZE'd2;
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd2;
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end else if(INSTRUCTION_ADDRESS[0:0]==0)begin
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INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
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/* verilator lint_off BLKSEQ */
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FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
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end else begin
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INPUT_FIFO[FIFO_end] <= external_data_bus[15:8];
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/* verilator lint_off BLKSEQ */
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FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
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end
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biu_state <= `BIU_NEXT_ACTION;
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read<=1;
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end
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/*************** DATA WRITE ***************/
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//TODO TODO TODO flush fifo, self modifying code
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`BIU_PUT_UNALIGNED_16BIT_DATA:begin
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`ifdef DEBUG_DATA_READ_WRITES
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$display("Writing 16bit %04x at %04x",DATA,DATA_ADDRESS);
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`endif
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BHE <= 0;
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data_bus_output_register <= {DATA[7:0],DATA[15:8]};
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write <= 0;
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biu_state <= `BIU_PUT_UNALIGNED_PREP_NEXT2;
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end
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`BIU_PUT_UNALIGNED_PREP_NEXT2:begin
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write <= 1;
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DATA_ADDRESS <= DATA_ADDRESS+20'd1;
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BHE <= 1;
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biu_state <= `BIU_WRITE_EXIT;
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end
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`BIU_PUT_ALIGNED_16BIT_DATA:begin
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`ifdef DEBUG_DATA_READ_WRITES
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$display("Writing 16bit %04x at %04x",DATA,DATA_ADDRESS);
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`endif
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data_bus_output_register <= {DATA[15:8],DATA[7:0]};
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write <= 0;
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biu_state <= `BIU_WRITE_RELEASE;
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end
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`BIU_PUT_BYTE:begin
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`ifdef DEBUG_DATA_READ_WRITES
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$display("Writing 8bit %02x at %04x",DATA[7:0],DATA_ADDRESS);
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`endif
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if(ADDRESS_INPUT[0:0]==0) begin
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BHE <= 1;
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data_bus_output_register <= {8'b0,DATA[7:0]};
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end else begin
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BHE <= 0;
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data_bus_output_register <= {DATA[7:0],8'b0};
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end
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write <= 0;
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biu_state <= `BIU_WRITE_RELEASE;
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end
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`BIU_WRITE_EXIT:begin
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write <= 0;
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biu_state <= `BIU_WRITE_RELEASE;
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end
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`BIU_WRITE_RELEASE:begin
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write <= 1;
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biu_state <= `BIU_NEXT_ACTION;
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end
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/*************** DATA READ ***************/
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`define finished_read \
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DATA_DIR <= 0; \
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if ( read_request == 0 ) begin \
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biu_state <= `BIU_NEXT_ACTION;\
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VALID_DATA <= 0;\
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end else \
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VALID_DATA <= 1;
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`BIU_GET_ALIGNED_DATA:begin
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`ifdef DEBUG_DATA_READ_WRITES
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if(Wbit==1)
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$display("Reading 16bit %04x from %04x",external_data_bus,DATA_ADDRESS);
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else
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$display("Reading 8bit %02x from %04x",external_data_bus[7:0],DATA_ADDRESS);
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`endif
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DATA_OUT <= (Wbit==1)? external_data_bus : {8'b0,external_data_bus[7:0]} ;
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read <=1;
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`finished_read
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end
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`BIU_GET_UNALIGNED_DATA:begin
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`ifdef DEBUG_DATA_READ_WRITES
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if(Wbit==0)
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$display("Reading 8bit %02x from %04x",external_data_bus[15:8],DATA_ADDRESS);
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`endif
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DATA_OUT[7:0] <= external_data_bus[15:8];
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read <=1;
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if(Wbit==1) begin
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biu_state <= `BIU_GET_SECOND_BYTE;
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end else begin
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`finished_read
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end
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end
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`BIU_GET_SECOND_BYTE:begin
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DATA_ADDRESS <= DATA_ADDRESS+20'd1;
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biu_state <= `BIU_GET_SECOND_BYTE1;
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read <=0;
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end
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`BIU_GET_SECOND_BYTE1:begin
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`ifdef DEBUG_DATA_READ_WRITES
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$display("Reading 16bit %02x from %04x",{external_data_bus[7:0],DATA_OUT[7:0]},DATA_ADDRESS-1);//read started a byte earlier
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`endif
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DATA_OUT[15:8] <= external_data_bus[7:0];
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`finished_read
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read <=1;
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end
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/*************** HOUSE KEEPING ***************/
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`BIU_RESET: begin
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/* verilator lint_off BLKSEQ */
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FIFO_start = `L1_CACHE_SIZE'b0;
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FIFO_end = `L1_CACHE_SIZE'b0;
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/* verilator lint_on BLKSEQ */
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biu_state <= `BIU_NEXT_ACTION;
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INSTRUCTION_ADDRESS <= 20'h0FFF0;
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INSTRUCTION_LOCATION <= 16'hFFF0;
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VALID_INSTRUCTION <= 0;
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VALID_DATA <= 0;
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DATA_DIR <= 0;
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end
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default: begin
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biu_state <= `BIU_NEXT_ACTION;/*Should be unreachable*/
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end
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endcase
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end
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end
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wire [2:0] Isize;
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InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
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`ifdef INCLUDE_EARLY_CALC_CIRUIT
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wire [2:0] fifoIsize;
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wire Isit1;
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InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1][5:3]},fifoIsize);
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Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
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`endif
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`ifdef DOUBLE_INSTRUCTION_LOAD
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wire [2:0] fifoIsize2;
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InstrSize fifoInstrSize2(
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{ INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}][7:0], INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}+`L1_CACHE_SIZE'd1][5:3]}
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,fifoIsize2
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);
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`endif
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always @( valid_instruction_ack ) begin
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/* verilator lint_off BLKSEQ */
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FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
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`ifdef DOUBLE_INSTRUCTION_LOAD
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if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin
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if((fifoIsize2==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}))begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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end else if((fifoIsize2==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}))begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
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end else if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize})begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
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end else
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VALID_INSTRUCTION <= 0;
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end else begin
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VALID_INSTRUCTION <= 0;
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end
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`else
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VALID_INSTRUCTION <= 0;
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`endif
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end
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always @( posedge jump_req ) begin
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jump_req_latch <= 1;
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DATA_DIR <= 1;
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VALID_INSTRUCTION <= 0;
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end
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endmodule
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