105 lines
2.0 KiB
Verilog
105 lines
2.0 KiB
Verilog
`timescale 1ns/1ps
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module clock_gen (input enable, output reg clk);
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parameter FREQ = 1000; // in HZ
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parameter PHASE = 0; // in degrees
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parameter DUTY = 50; // in percentage
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real clk_pd = 1.0/FREQ * 1000000; // convert to ms
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real clk_on = DUTY/100.0 * clk_pd;
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real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
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real quarter = clk_pd/4;
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real start_dly = quarter * PHASE/90;
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reg start_clk;
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initial begin
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end
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// Initialize variables to zero
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initial begin
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clk <= 0;
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start_clk <= 0;
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end
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// When clock is enabled, delay driving the clock to one in order
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// to achieve the phase effect. start_dly is configured to the
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// correct delay for the configured phase. When enable is 0,
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// allow enough time to complete the current clock period
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always @ (posedge enable or negedge enable) begin
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if (enable) begin
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#(start_dly) start_clk = 1;
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end else begin
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#(start_dly) start_clk = 0;
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end
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end
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// Achieve duty cycle by a skewed clock on/off time and let this
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// run as long as the clocks are turned on.
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always @(posedge start_clk) begin
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if (start_clk) begin
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clk = 1;
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while (start_clk) begin
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#(clk_on) clk = 0;
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#(clk_off) clk = 1;
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end
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clk = 0;
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end
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end
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endmodule
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
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/* State */
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reg [1:0] state;
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reg start=0;
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reg instruction_finished;
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/* Registers */
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reg [19:0] ProgCount;
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/* RESET LOGIC */
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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state=0;
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ProgCount=0;//TODO: Reset Vector
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#10
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start=1;
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end
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end
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/* CLOCK LOGIC */
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always @(posedge clock) begin
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if(instruction_finished) begin
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state =0;
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end else begin
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if (clock && start==1) begin
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state=state+1;
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end
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end
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end
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always @(state) begin
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if (state==2) begin
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instruction_finished=1;
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end else begin
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instruction_finished=0;
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end
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end
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/* Processor stages */
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always @(state) begin
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if (state==0) begin
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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end
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end
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endmodule
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