756 lines
24 KiB
Verilog
756 lines
24 KiB
Verilog
/* decoder.v - Implementation of instruction opcode decoding logic
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "exec_state_def.v"
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`include "alu_header.v"
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`include "ucode_header.v"
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`include "error_header.v"
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module microcode(
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input [`UCODE_ADDR_BITS-1:0] ADDR,
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output [`UCODE_DATA_BITS-1:0] DATA
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);
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initial begin
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string ucode_path;
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if($value$plusargs("MICROCODE=%s",ucode_path))begin
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$readmemb(ucode_path,ucode_rom,0,`UCODE_SIZE-1);
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end else begin
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$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=<path>");
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$finish;
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end
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end
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reg [`UCODE_DATA_BITS-1:0] ucode_rom [ 0:`UCODE_SIZE-1 ];
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assign DATA=ucode_rom[ADDR];
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endmodule
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module decoder(
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/* INPUTS */ input wire [15:0] CIR,input wire [15:0] FLAGS
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/* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
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/* OUTPUT */ ,output wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] OUTPUT, output reg DEPENDS_ON_PREVIOUS
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);
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/* DEPENDS_ON_PREVIOUS - This encodes weather the instruction requires the previous to be finished in order to be decoded. This, for example, affects
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* conditional jumps since flags are checked during decode.
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*/
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reg [2:0]IN_MOD;
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assign OUTPUT[2:0] = IN_MOD;
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reg [2:0]RM;
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assign OUTPUT[5:3] = RM;
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reg memio_address_select;
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assign OUTPUT[6:6] = memio_address_select;
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reg MEM_OR_IO;
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assign OUTPUT[7:7] = MEM_OR_IO;
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reg [15:0] PARAM1;
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assign OUTPUT[23:8] = PARAM1;
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reg [15:0] PARAM2;
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assign OUTPUT[39:24] = PARAM2;
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reg [2:0]ALU_OP;
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assign OUTPUT[42:40] = ALU_OP;
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reg [1:0]in_alu_sel1;
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assign OUTPUT[44:43] = in_alu_sel1;
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reg [1:0]in_alu_sel2;
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assign OUTPUT[46:45] = in_alu_sel2;
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reg [2:0]OUT_MOD;
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assign OUTPUT[49:47] = OUT_MOD;
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reg [3:0]reg_read_port1_addr;
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assign OUTPUT[53:50] = reg_read_port1_addr;
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reg [3:0]reg_read_port2_addr;
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assign OUTPUT[57:54] = reg_read_port2_addr;
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reg [3:0]reg_write_addr;
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assign OUTPUT[61:58] = reg_write_addr;
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reg Wbit,Sbit,opcode_size;
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assign OUTPUT[64:62] = {Wbit,Sbit,opcode_size};
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reg [`ERROR_BITS-1:0] ERROR;
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reg HALT;
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assign OUTPUT[`ERROR_BITS+65:65]={ERROR,HALT};
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reg [`EXEC_STATE_BITS-1:0] next_state;
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assign OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66] = next_state;
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/* verilator lint_off UNUSEDSIGNAL */
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wire [`UCODE_DATA_BITS-1:0] ucode_data;
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/* verilator lint_on UNUSEDSIGNAL */
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microcode ucode(seq_addr_input,ucode_data);
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`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
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//TODO: A possible optimisation for instruction with 8bit parameter and
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//opcode_size=0 would be to set PARAM1 here instead of sending execution over
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//to EXEC_DE_LOAD_8_PARAM
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`define normal_instruction seq_addr_entry<=`UCODE_NO_INSTRUCTION;ERROR<=`ERR_NO_ERROR;HALT<=0;MEM_OR_IO=0;
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`define normal_microcoded ERROR<=`ERR_NO_ERROR;HALT<=0;MEM_OR_IO=0;
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// I use blocking for basically putting names on the different fields of CIR and
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// then branching off of that instead of the raw bits. otherwise the code
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// would be identical
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// verilator lint_off BLKSEQ
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always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
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if (SIMPLE_MICRO==0)begin
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casez({CIR[15:8],CIR[5:3]})
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11'b0000_010?_??? : begin
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/* ADD - Add Immediate word/byte to accumulator */
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/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
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opcode_size=0;
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Wbit=CIR[8:8];
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IN_MOD=3'b011;
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in_alu_sel1=2'b00;
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in_alu_sel2=2'b01;
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OUT_MOD=3'b011;
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MEM_OR_IO=0;
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reg_read_port2_addr={Wbit,3'b000};
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reg_write_addr={Wbit,3'b000};
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ALU_OP=`ALU_OP_ADD;
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memio_address_select=0;
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if(Wbit)
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next_state=`EXEC_DE_LOAD_16_PARAM;
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else
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next_state=`EXEC_DE_LOAD_8_PARAM;
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DEPENDS_ON_PREVIOUS<=0;
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`normal_instruction;
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end
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11'b1000_00??_101, /* SUB */
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11'b1000_00??_000 : /* ADD */ begin
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/* ADD - Add Immediate word/byte to register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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/* SUB - Subtract immediate word/byte from register/memory */
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/* 1 0 0 0 0 0 S W | MOD 1 0 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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IN_MOD={1'b0,CIR[7:6]};
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RM=CIR[2:0];
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in_alu_sel1=2'b00;
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if(IN_MOD==3'b011)begin
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in_alu_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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end else begin
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in_alu_sel2=2'b00;
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end
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OUT_MOD=IN_MOD;
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MEM_OR_IO=0;
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memio_address_select=0;
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case({Sbit,Wbit})
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2'b00,2'b11:begin
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next_state=`EXEC_DE_LOAD_8_PARAM;
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end
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2'b01:begin
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next_state=`EXEC_DE_LOAD_16_PARAM;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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case(CIR[5:3])
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3'b000: ALU_OP=`ALU_OP_ADD;
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3'b101: ALU_OP=`ALU_OP_SUB_REVERSE;
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default:begin
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/*Should be impossible*/
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`invalid_instruction
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end
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endcase
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DEPENDS_ON_PREVIOUS<=0;
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`normal_instruction;
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end
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11'b1000_00??_111 : begin
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/* CMP - compare Immediate with register / memory */
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/* 1 0 0 0 0 0 S W | MOD 1 1 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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IN_MOD={1'b0,CIR[7:6]};
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RM=CIR[2:0];
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if ( {Sbit,Wbit} == 2'b10 )begin
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`invalid_instruction
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end
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in_alu_sel1=2'b00;
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OUT_MOD=3'b100;
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MEM_OR_IO=0;
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ALU_OP=`ALU_OP_SUB;
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memio_address_select=0;
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if(IN_MOD==3'b011)begin
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/*compare register with param*/
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in_alu_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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next_state=`EXEC_DE_LOAD_8_PARAM;
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end else begin
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/*compare register indirect access
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* with param */
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in_alu_sel2=2'b00;
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next_state=`EXEC_DE_LOAD_16_PARAM; /*will then call MEMIO_READ*/
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end
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DEPENDS_ON_PREVIOUS<=0;
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`normal_instruction;
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end
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11'b1011_0???_??? : begin
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/* MOV - Move Immediate byte to register */
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/* 1 0 1 1 W REG | DATA | DATA if W |*/
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Wbit=CIR[11:11]; /* IS 0 */
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opcode_size=0;
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IN_MOD=3'b011;
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in_alu_sel1=2'b00;
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in_alu_sel2=2'b00;
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OUT_MOD=3'b011;
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MEM_OR_IO=0;
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reg_write_addr={1'b0,CIR[10:8]};
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PARAM1[7:0]=CIR[7:0];
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PARAM2=0;
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ALU_OP=`ALU_OP_ADD;
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next_state=`EXEC_WRITE_ENTRY;
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b1011_1???_??? : begin
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/*MOV - Move Immediate word to register*/
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Wbit=CIR[11:11]; /*IS 1 */
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opcode_size=0;
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IN_MOD=3'b011;
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in_alu_sel1=2'b00;
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in_alu_sel2=2'b00;
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OUT_MOD=3'b011;
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MEM_OR_IO=0;
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reg_write_addr={1'b1,CIR[10:8]};
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ALU_OP=`ALU_OP_ADD;
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PARAM2=0;
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next_state=`EXEC_DE_LOAD_16_PARAM;
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b1000_10??_??? : begin
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/* MOV - Reg/Mem to/from register */
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/* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/
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opcode_size=1;
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RM=CIR[2:0];
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Wbit=CIR[8:8];
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in_alu_sel1=2'b00;
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PARAM1=0;
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MEM_OR_IO=0;
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if(CIR[9:9] == 1)begin
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/* Mem/Reg to reg */
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IN_MOD={1'b0,CIR[7:6]};
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if(IN_MOD==3'b011)begin
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/*Reg to Reg*/
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in_alu_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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next_state=`EXEC_WRITE_ENTRY;
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end else begin
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/*Mem to Reg*/
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in_alu_sel2=2'b00;
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next_state=`EXEC_MEMIO_READ;
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end
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OUT_MOD=3'b011;
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reg_write_addr={Wbit,CIR[5:3]};
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end else begin
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/* Reg to Mem/Reg */
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IN_MOD=3'b011;
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OUT_MOD={1'b0,CIR[7:6]};
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if(IN_MOD==3'b011)begin
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/*Reg to Reg*/
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in_alu_sel2=2'b01;
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reg_write_addr={Wbit,RM};
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next_state=`EXEC_WRITE_ENTRY;
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end else begin
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/*Reg to Mem*/
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in_alu_sel2=2'b00;
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next_state=`EXEC_DE_LOAD_REG_TO_PARAM;
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end
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reg_read_port2_addr={Wbit,CIR[5:3]};
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end
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ALU_OP=`ALU_OP_ADD;
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b0100_????_???:begin//DEC
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/* DEC - Decrement Register */
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/* | 0 1 0 0 1 REG | */
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/* INC - Increment Register */
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/* | 0 1 0 0 0 REG | */
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opcode_size=0;
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Wbit=1;
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in_alu_sel1=2'b01;
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in_alu_sel2=2'b00;
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OUT_MOD=3'b011;
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MEM_OR_IO=0;
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IN_MOD=3'b011;
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PARAM2=1;
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reg_read_port1_addr={1'b1,CIR[10:8]};
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reg_write_addr={1'b1,CIR[10:8]};
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if(CIR[11:11]==0)
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ALU_OP=`ALU_OP_ADD;
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else
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ALU_OP=`ALU_OP_SUB;
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next_state=`EXEC_WRITE_ENTRY;
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b1111_111?_00? : begin
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/* INC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
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/* DEC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
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opcode_size=1;
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Wbit=CIR[8:8];
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IN_MOD={1'b0,CIR[7:6]};
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RM=CIR[2:0];
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in_alu_sel2=(IN_MOD==3'b011)? 2'b01 : 2'b00;
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in_alu_sel1=2'b00;/* number 1 */
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PARAM1=1;
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OUT_MOD=IN_MOD;
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MEM_OR_IO=0;
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/*in case IN_MOD=011 */
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reg_read_port2_addr={1'b0,RM};
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reg_write_addr={1'b0,RM};
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ALU_OP=(CIR[3:3]==1)?`ALU_OP_SUB_REVERSE:`ALU_OP_ADD;
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if ( IN_MOD == 3'b011 )
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next_state=`EXEC_WRITE_ENTRY;
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else
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next_state=`EXEC_MEMIO_READ;
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b1111_0100_??? : begin
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/* HLT - Halt */
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/* 1 1 1 1 0 1 0 0 | */
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opcode_size=0;
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IN_MOD=3'b011;
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HALT<=1;
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ERROR<=`ERR_NO_ERROR;
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MEM_OR_IO=0;
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seq_addr_entry<=`UCODE_NO_INSTRUCTION;
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next_state=`EXEC_WAIT;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b0011_110?_??? : begin
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/* CMP - Compare Immediate with accumulator */
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/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
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/* */
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/* NOTE: 8086 doc doesn't show the third byte but the */
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/* W flag and my assembler seem to disagree */
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Wbit=CIR[8:8];
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opcode_size=0;
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IN_MOD=3'b011;
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in_alu_sel1=2'b00;
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in_alu_sel2=2'b01;
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reg_read_port2_addr={Wbit,3'b000};
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OUT_MOD=3'b100;
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ALU_OP=`ALU_OP_SUB;
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MEM_OR_IO=0;
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if(Wbit==1)
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next_state=`EXEC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`EXEC_WRITE_ENTRY;
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end
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=0;
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memio_address_select=0;
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end
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11'b0111_????_???:begin
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/* Conditional relative jumps */
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/* JE/JZ - Jump on Zero */
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/* 0 1 1 1 0 1 0 0 | IP-INC8 |*/
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/* JS - Jump on Sign */
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/* 0 1 1 1 1 0 0 0 | IP-INC8 |*/
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/* JNS -Jump on not Sign */
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/* 0 1 1 1 1 0 0 1 | IP-INC8 |*/
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/* .... */
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Wbit=1;
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opcode_size=0;
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in_alu_sel1=2'b10;
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in_alu_sel2=2'b00;
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PARAM2={{8{CIR[7:7]}},CIR[7:0]};
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ALU_OP=`ALU_OP_ADD_SIGNED_B;
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MEM_OR_IO=0;
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OUT_MOD=3'b101;
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case(CIR[11:9])
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3'b000: begin
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/* Jump on (not) Overflow */
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if(FLAGS[11:11]==CIR[8:8])
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next_state=`EXEC_NEXT_INSTRUCTION;
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else begin
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next_state=`EXEC_WRITE_ENTRY;
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end
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end
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3'b010: begin
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/* Jump on (not) Zero */
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if(FLAGS[6:6]==CIR[8:8])
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next_state=`EXEC_NEXT_INSTRUCTION;
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else
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next_state=`EXEC_WRITE_ENTRY;
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end
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3'b100: begin
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/* Jump on (not) Sign */
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if(FLAGS[7:7]==CIR[8:8])
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next_state=`EXEC_NEXT_INSTRUCTION;
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else
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next_state=`EXEC_WRITE_ENTRY;
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end
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3'b101: begin
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/* Jump on (not) Parity */
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if(FLAGS[2:2]==CIR[8:8])
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next_state=`EXEC_NEXT_INSTRUCTION;
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else
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next_state=`EXEC_WRITE_ENTRY;
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end
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default:begin
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`invalid_instruction; /*We don't support that condition*/
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end
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endcase
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`normal_instruction;
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DEPENDS_ON_PREVIOUS<=1;
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memio_address_select=0;
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end
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11'b1110_1011_???:begin
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/* JMP - Unconditional jump direct within segment (short) */
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/* | 1 1 1 0 1 0 1 1 | IP-INC-LO | */
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opcode_size=0;
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Wbit=1;
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in_alu_sel1=2'b10;
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in_alu_sel2=2'b00;
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PARAM2={{8{CIR[7:7]}},CIR[7:0]};
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ALU_OP=`ALU_OP_ADD_SIGNED_B;
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OUT_MOD=3'b101;
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MEM_OR_IO=0;
|
|
next_state=`EXEC_WRITE_ENTRY;
|
|
`normal_instruction;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1110_1000_???:begin
|
|
/* CALL - Direct call within segment */
|
|
/* 1 1 1 0 1 0 0 0 | IP-INC-LO | IP-INC-HI |*/
|
|
|
|
// Microcode instruction
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=1;
|
|
PARAM2=2; //subtract from sp
|
|
seq_addr_entry<=`UCODE_CALL_ENTRY;
|
|
`normal_microcoded
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1100_0011_???:begin
|
|
/* RET - Return from call within segment */
|
|
/* | 1 1 0 0 0 0 1 1 | */
|
|
|
|
// Microcode instruction
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=0;
|
|
PARAM1=2;
|
|
seq_addr_entry<=`UCODE_RET_ENTRY;
|
|
`normal_microcoded
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1010_101?_???:begin
|
|
/* STOS - Write byte/word to [DI] and increment accordingly */
|
|
/* | 1 0 1 0 1 0 1 W | */
|
|
opcode_size=0;
|
|
Wbit=CIR[8:8];
|
|
Sbit=0;
|
|
RM=3'b101;
|
|
seq_addr_entry<=`UCODE_STOS_ENTRY;
|
|
`normal_microcoded
|
|
PARAM2=(Wbit==1)?2:1;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b0101_0???_???:begin
|
|
/* PUSH - SP-=2; [SP]=REG */
|
|
/* | 0 1 0 1 0 REG | */
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=0;
|
|
PARAM2=2;
|
|
reg_read_port2_addr={1'b1,CIR[10:8]};
|
|
seq_addr_entry<=`UCODE_PUSH_ENTRY;
|
|
`normal_microcoded
|
|
memio_address_select=0;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
end
|
|
11'b1111_011?_000:begin
|
|
/* TEST - Bitwise AND affecting only flags */
|
|
/* 1 1 1 1 0 1 1 W | MOD 0 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */
|
|
opcode_size=1;
|
|
Wbit=CIR[8:8];
|
|
IN_MOD={1'b0,CIR[7:6]};
|
|
RM={CIR[2:0]};
|
|
MEM_OR_IO=0;
|
|
if(Wbit==1)begin
|
|
next_state=`EXEC_DE_LOAD_16_PARAM;
|
|
end else begin
|
|
next_state=`EXEC_DE_LOAD_8_PARAM;
|
|
end
|
|
in_alu_sel1=2'b00; /* PARAM1 */
|
|
ALU_OP=`ALU_OP_AND;
|
|
case(IN_MOD)
|
|
3'b011:begin
|
|
in_alu_sel2=2'b01;
|
|
reg_read_port2_addr={Wbit,RM};
|
|
end
|
|
default:begin
|
|
`invalid_instruction
|
|
end
|
|
endcase
|
|
OUT_MOD=3'b100;/*NULL*/
|
|
`normal_instruction;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b0101_1???_???:begin
|
|
/* POP - REG=[SP]; SP+=2 */
|
|
/* | 0 1 0 1 1 REG | */
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=0;
|
|
PARAM1=2;
|
|
reg_write_addr={1'b1,CIR[10:8]};
|
|
seq_addr_entry<=`UCODE_POP_ENTRY;
|
|
`normal_microcoded
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1111_1111_100:begin
|
|
/* JMP - Unconditional indirect within segment jump */
|
|
/* 1 1 1 1 1 1 1 1 | MOD 1 0 0 R/M | < DISP-LO > | < DISP-HI > */
|
|
opcode_size=1;
|
|
Wbit=1;
|
|
IN_MOD={1'b0,CIR[7:6]};
|
|
RM=CIR[2:0];
|
|
MEM_OR_IO=0;
|
|
in_alu_sel1=2'b11;
|
|
if (IN_MOD==3'b011)begin
|
|
in_alu_sel2=2'b01;
|
|
reg_read_port2_addr={Wbit,RM};
|
|
next_state=`EXEC_WRITE_ENTRY;
|
|
end else begin
|
|
in_alu_sel2=2'b00;
|
|
next_state=`EXEC_MEMIO_READ;
|
|
end
|
|
ALU_OP=`ALU_OP_ADD;
|
|
OUT_MOD=3'b101;
|
|
`normal_instruction;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1100_011?_000:begin
|
|
/* MOV - Move immediate to register/memory */
|
|
/* 1 1 0 0 0 1 1 W | MOD 0 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */
|
|
Wbit=CIR[8:8];
|
|
opcode_size=1;
|
|
in_alu_sel1=2'b00;
|
|
in_alu_sel2=2'b11;
|
|
MEM_OR_IO=0;
|
|
if(Wbit==1)begin
|
|
next_state=`EXEC_DE_LOAD_16_PARAM;
|
|
end else begin
|
|
next_state=`EXEC_DE_LOAD_8_PARAM;
|
|
end
|
|
|
|
OUT_MOD={1'b0,CIR[7:6]};
|
|
IN_MOD=3'b011;
|
|
RM=CIR[2:0];
|
|
`normal_instruction;
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1100_1101_???:begin
|
|
/* INT - execute interrupt handler */
|
|
/* 1 1 0 0 1 1 0 1 | DATA |*/
|
|
// [skipped] 1) push flags
|
|
// [skipped] 2) clear trap and interrupt enable flag
|
|
// [skipped] 3) push CS
|
|
// [skipped] 4) fetch CS from interrupt table
|
|
// 5) push ProgCount
|
|
// 6) fetch ProgCount from interrupt table
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=0;
|
|
PARAM2=2;
|
|
seq_addr_entry<=`UCODE_INT_ENTRY;
|
|
`normal_microcoded
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
11'b1110_011?_???:begin
|
|
/* OUT - write AL or AX to a defined output port */
|
|
/* | 1 1 1 0 0 1 1 W | DATA 8 | */
|
|
memio_address_select=1;
|
|
Wbit=CIR[8:8];
|
|
opcode_size=0;
|
|
in_alu_sel1=2'b00;
|
|
in_alu_sel2=2'b11;
|
|
reg_read_port1_addr={Wbit,3'b000};
|
|
next_state=`EXEC_DE_LOAD_8_PARAM;
|
|
MEM_OR_IO=1;
|
|
HALT <= 0;
|
|
PARAM1=0;
|
|
OUT_MOD={3'b000};
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
IN_MOD=3'b011;
|
|
end
|
|
11'b1100_1111_???:begin
|
|
/* IRET - Return from interrupt */
|
|
/* | 1 1 0 0 1 1 1 1 | */
|
|
// Since we only push one thing on the stack
|
|
// on INT we can just reuse the code from RET
|
|
opcode_size=0;
|
|
Wbit=1;
|
|
Sbit=0;
|
|
PARAM1=2;
|
|
seq_addr_entry<=`UCODE_RET_ENTRY;
|
|
`normal_microcoded
|
|
DEPENDS_ON_PREVIOUS<=0;
|
|
memio_address_select=0;
|
|
end
|
|
default:begin
|
|
`invalid_instruction
|
|
end
|
|
endcase
|
|
end else begin
|
|
/*Microcode output*/
|
|
//Sbit, Wbit, opcode_size and the others are still latched
|
|
//from when we ordered the switch to microcode
|
|
seq_addr_entry <= ucode_data[`UCODE_ADDR_BITS-1:0];
|
|
case(ucode_data[8:6])
|
|
3'b000: next_state=`EXEC_WRITE_ENTRY;
|
|
3'b001: next_state=`EXEC_DE_LOAD_16_PARAM;
|
|
3'b010: next_state=`EXEC_DE_LOAD_8_PARAM;
|
|
3'b011: next_state=`EXEC_MEMIO_READ;
|
|
3'b100: next_state=`EXEC_MEMIO_READ_SETADDR;
|
|
default: begin end /*impossible*/
|
|
endcase
|
|
if(ucode_data[36:36]==0) /*Set reg write address*/
|
|
reg_write_addr = ucode_data[12:9 ];
|
|
in_alu_sel1 = ucode_data[14:13];
|
|
in_alu_sel2 = ucode_data[16:15];
|
|
OUT_MOD = ucode_data[19:17];
|
|
/*1:1 map essentially but I want to keep the spec for these bits separate
|
|
* from the alu op select bits*/
|
|
case(ucode_data[22:20])
|
|
3'b000: ALU_OP=`ALU_OP_ADD;
|
|
3'b001: ALU_OP=`ALU_OP_SUB;
|
|
3'b010: ALU_OP=`ALU_OP_AND;
|
|
3'b011: ALU_OP=`ALU_OP_OR;
|
|
3'b100: ALU_OP=`ALU_OP_XOR;
|
|
3'b101: ALU_OP=`ALU_OP_ADD_SIGNED_B;
|
|
3'b110: ALU_OP=`ALU_OP_SUB_REVERSE;
|
|
3'b111: ALU_OP=`ALU_OP_SHIFT_LEFT;
|
|
default: begin end
|
|
endcase
|
|
if(ucode_data[34:34]==0) /* Set reg read port 1 address */
|
|
reg_read_port1_addr=ucode_data[26:23];
|
|
IN_MOD=ucode_data[29:27];
|
|
if(ucode_data[35:35]==0) /* Set reg read port 1 address */
|
|
reg_read_port2_addr=ucode_data[33:30];
|
|
if(ucode_data[37:37]==1) /* Overwrite Wbit */
|
|
Wbit=ucode_data[38:38];
|
|
memio_address_select=ucode_data[39:39];
|
|
MEM_OR_IO=0;
|
|
HALT <= 0;
|
|
end
|
|
end
|
|
`undef invalid_instruction
|
|
|
|
endmodule
|
|
// verilator lint_on BLKSEQ
|
|
|
|
|
|
/* IN: {CIR[15:8],CIR[5:3]} */
|
|
/* OUT: number in bytes */
|
|
module InstrSize ( input [10:0] IN, output reg [2:0] VERDICT );
|
|
always @( IN ) begin
|
|
casez(IN)
|
|
11'b0000_010?_??? : VERDICT <= 3'd2+{2'b0,IN[3:3]}; /* ADD - Add Immediate word/byte to accumulator */
|
|
11'b1000_00??_101 : VERDICT <= 3'd3+{2'b0,(IN[4:3]==2'b01)}; /* SUB - Subtract immediate word/byte from register/memory */
|
|
11'b1000_00??_000 : VERDICT <= 3'd3+{2'b0,(IN[4:3]==2'b01)}; /* ADD - Add Immediate word/byte to register/memory */
|
|
11'b1000_00??_111 : VERDICT <= 3'd3+{2'b0,(IN[4:3]==2'b01)}; /* CMP - compare Immediate with register / memory */
|
|
11'b1011_????_??? : VERDICT <= 3'd2+{2'b0,IN[6:6]}; /* MOV - Move Immediate byte to register */
|
|
11'b1000_10??_??? : VERDICT <= 3'd2; /* MOV - Reg/Mem to/from register */
|
|
11'b0100_????_??? : VERDICT <= 3'd1; /* DEC - Decrement Register | INC - Increment Register */
|
|
11'b1111_111?_00? : VERDICT <= 3'd2; /* INC - Register/Memory | DEC - Register/Memory */
|
|
11'b1111_0100_??? : VERDICT <= 3'd1; /* HLT - Halt */
|
|
11'b0011_110?_??? : VERDICT <= 3'd2+{2'b0,IN[3:3]}; /* CMP - Compare Immediate with accumulator */
|
|
11'b0111_????_??? : VERDICT <= 3'd2; /* Conditional relative jumps ( JE/JZ, JS/JNS ... ) */
|
|
11'b1110_1011_??? : VERDICT <= 3'd2; /* JMP - Unconditional jump direct within segment (short) */
|
|
11'b1110_1000_??? : VERDICT <= 3'd3; /* CALL - Direct call within segment */
|
|
11'b1100_0011_??? : VERDICT <= 3'd1; /* RET - Return from call within segment */
|
|
11'b1010_101?_??? : VERDICT <= 3'd1; /* STOS - Write byte/word to [DI] and increment accordingly */
|
|
11'b0101_0???_??? : VERDICT <= 3'd1; /* PUSH - SP-=2; [SP]=REG */
|
|
11'b1111_011?_000 : VERDICT <= 3'd3+{2'b0,IN[3:3]}; /* TEST - Bitwise AND affecting only flags */
|
|
11'b0101_1???_??? : VERDICT <= 3'd1; /* POP - REG=[SP]; SP+=2 */
|
|
11'b1111_1111_100 : VERDICT <= 3'd2; /* JMP - Unconditional indirect within segment jump */
|
|
11'b1100_011?_000 : VERDICT <= 3'd3+{2'b0,IN[3:3]}; /* MOV - Move immediate to register/memory */
|
|
11'b1100_1101_??? : VERDICT <= 3'd2; /* INT - execute interrupt handler */
|
|
11'b1110_011?_??? : VERDICT <= 3'd2; /* OUT - write AL or AX to a defined output port */
|
|
11'b1100_1111_??? : VERDICT <= 3'd1; /* IRET - Return from interrupt */
|
|
default:begin end
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
`ifdef INCLUDE_EARLY_CALC_CIRUIT
|
|
module Is1 ( input [7:0] IN, output reg VERDICT );
|
|
always @( IN ) begin
|
|
casez(IN)
|
|
8'b0100_???? : VERDICT <= 1; /* DEC - Decrement Register | INC - Increment Register */
|
|
8'b1111_0100 : VERDICT <= 1; /* HLT - Halt */
|
|
8'b1100_0011 : VERDICT <= 1; /* RET - Return from call within segment */
|
|
8'b1010_101? : VERDICT <= 1; /* STOS - Write byte/word to [DI] and increment accordingly */
|
|
8'b0101_0??? : VERDICT <= 1; /* PUSH - SP-=2; [SP]=REG */
|
|
8'b0101_1??? : VERDICT <= 1; /* POP - REG=[SP]; SP+=2 */
|
|
8'b1100_1111 : VERDICT <= 1; /* IRET - Return from interrupt */
|
|
default:begin VERDICT<= 0; end
|
|
endcase
|
|
end
|
|
endmodule
|
|
`endif
|