29 lines
720 B
Verilog
29 lines
720 B
Verilog
`include "alu_header.v"
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module ALU(input [15:0]A,input [15:0]B, input oe,output reg [15:0]OUT,input [`ALU_OP_BITS-1:0]op,output wire [7:0]FLAGS,input Wbit);
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reg C_FLAG;
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assign FLAGS={(Wbit==1)?OUT[15:15]:OUT[7:7],(Wbit==1) ? (OUT[15:0]=='h0000) : (OUT[7:0]=='h00),5'b00000,C_FLAG};
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always @ ( * ) begin
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if(Wbit==1)begin
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case (op)
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`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
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`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
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`ALU_OP_AND: OUT=A&B;
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`ALU_OP_OR: OUT=A|B;
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`ALU_OP_XOR: OUT=A^B;
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endcase
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end else begin
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case (op)
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`ALU_OP_ADD: {C_FLAG,OUT[7:0]}=A[7:0]+B[7:0];
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`ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0];
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`ALU_OP_AND: OUT=A&B;
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`ALU_OP_OR: OUT=A|B;
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`ALU_OP_XOR: OUT=A^B;
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endcase
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end
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end
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endmodule
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