347 lines
6.8 KiB
Verilog
347 lines
6.8 KiB
Verilog
/* I2C_driver.v - Implements an I2C interface
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module I2C_driver (
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input wire clock,
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input wire SDA_input,
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output reg SDA_output,
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output reg SDA_direction, //1:output 0:input
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output reg SCL,
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input wire [6:0] address,
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output reg I2C_BUSY=0,
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input wire I2C_TRANSACT,
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input wire DIR,
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input wire [15:0] i2c_data_write,
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input wire transact_width, /* 0=byte 1=word */
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/* verilator lint_off UNUSEDSIGNAL */
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input wire ignore_ack,
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/* verilator lint_on UNUSEDSIGNAL */
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output reg [15:0] i2c_data_read=16'h4141,
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output reg error=0
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);
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//assign i2c_data_read=16'h0042;
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reg DIR_latched;
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reg [5:0] i2c_state = 6'b100100;
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reg [3:0] data_bit_counter;
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reg [15:0] data_internal;
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reg [6:0]address_internal;
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reg trans_width_latch;
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always @(posedge clock) begin
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case (i2c_state)
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/***** start sequence ******/
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6'b000000:begin
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SDA_direction<=1;
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SDA_output<=1;
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SCL<=1;
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i2c_state<=6'b000001;
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end
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6'b000001:begin
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SDA_output<=0;
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SCL<=1;
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i2c_state<=6'b000010;
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end
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6'b000010:begin
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SDA_output<=0;
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SCL<=0;
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i2c_state<=6'b000011;
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data_bit_counter<=0;
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end
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/****** Set address ********/
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6'b000011:begin
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SCL<=0;
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i2c_state<=6'b000100;
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end
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6'b000100:begin
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SCL<=0;
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SDA_output<=address_internal[6:6];
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address_internal[6:0]<={address_internal[5:0],1'b0};
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b000101;
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end
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6'b000101:begin
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SCL<=1;
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i2c_state<=6'b000110;
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end
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6'b000110:begin
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SCL<=1;
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if(data_bit_counter==4'd7)
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i2c_state<=6'b000111;
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else
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i2c_state<=6'b000011;
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end
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/****** Read/Write *********/
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6'b000111:begin
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SCL<=0;
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i2c_state<=6'b001000;
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end
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6'b001000:begin
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SCL<=0;
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SDA_output<=DIR_latched;/*Write=0 Read=1*/
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i2c_state<=6'b001001;
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end
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6'b001001:begin
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SCL<=1;
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i2c_state<=6'b001010;
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end
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6'b001010:begin
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SCL<=1;
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i2c_state<=6'b001011;
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end
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/****** Acknowledge ********/
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6'b001011:begin
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SCL<=0;
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SDA_direction<=0;
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i2c_state<=6'b001100;
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end
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6'b001100:begin
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SCL<=0;
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i2c_state<=6'b001101;
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end
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6'b001101:begin
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SCL<=1;
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i2c_state<=6'b001110;
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end
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6'b001110:begin
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SCL<=1;
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if (SDA_input==1)begin
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error<=1'b1;
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i2c_state<=6'b100100;
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end
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i2c_state<=6'b001111;
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data_bit_counter<=0;
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end
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/****** separator ********/
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6'b001111:begin
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SCL<=0;
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SDA_output<=0;
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i2c_state<=6'b010000;
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end
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6'b010000:begin
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SCL<=0;
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i2c_state<=6'b010001;
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end
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6'b010001:begin
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SCL<=0;
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SDA_output<=1;
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i2c_state<=6'b010010;
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end
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6'b010010:begin
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SCL<=0;
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SDA_output<=1;
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i2c_state<=6'b010011;
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end
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6'b010011:begin
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SCL<=0;
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SDA_output<=0;
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i2c_state<=6'b010100;
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end
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/****** Send data ********/
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6'b010100:begin
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if(DIR_latched==1'b1)begin
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SDA_direction<=0;
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end else begin
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SDA_direction<=1;
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end
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SCL<=0;
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i2c_state<=6'b010101;
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end
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6'b010101:begin
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SCL<=0;
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if(DIR_latched==1'b0)begin
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SDA_output<=data_internal[7:7];
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data_internal[7:0]<={data_internal[6:0],1'b0};
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end
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b010110;
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end
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6'b010110:begin
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SCL<=1;
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if(DIR_latched==1'b1)begin
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i2c_data_read[15:0]<={8'h0,i2c_data_read[6:0],SDA_input};
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end
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i2c_state<=6'b010111;
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end
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6'b010111:begin
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SCL<=1;
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if(data_bit_counter==4'd8)begin
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i2c_state<=6'b011000;
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end else begin
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i2c_state<=6'b010100;
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end
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end
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/****** Acknowledge ********/
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6'b011000:begin
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// Note: If we read we want to send an ack,
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// If we write we want to read an ack so it's reversed here
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if(DIR_latched==1'b1)begin
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SDA_direction<=1;
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end else begin
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SDA_direction<=0;
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end
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SCL<=0;
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i2c_state<=6'b011001;
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end
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6'b011001:begin
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SCL<=0;
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if(DIR_latched==1'b1)begin
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SDA_output<=1'b0;
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end
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i2c_state<=6'b011010;
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end
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6'b011010:begin
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SCL<=1;
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i2c_state<=6'b011011;
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end
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6'b011011:begin
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SCL<=1;
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if (SDA_input==1 && DIR_latched==1'b0)begin
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error<=1'b1;
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end
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if(trans_width_latch==1'b1)begin
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i2c_state<=6'b100101;
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data_bit_counter<=4'd0;
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end else
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i2c_state<=6'b011100;
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end
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/****** Send data (16bit) ********/
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6'b100101:begin
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SCL<=0;
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if(DIR_latched==1'b1)begin
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SDA_direction<=0;
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end else begin
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SDA_direction<=1;
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end
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i2c_state<=6'b100110;
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end
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6'b100110:begin
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SCL<=0;
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if(DIR_latched==1'b0)begin
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SDA_output<=data_internal[15:15];
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data_internal[15:8]<={data_internal[14:8],1'b0};
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end
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b100111;
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end
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6'b100111:begin
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SCL<=1;
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if(DIR_latched==1'b1)begin
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i2c_data_read[15:0]<={i2c_data_read[14:8],SDA_input,i2c_data_read[7:0]};
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end
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i2c_state<=6'b101000;
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end
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6'b101000:begin
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SCL<=1;
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if(data_bit_counter==4'd8)begin
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i2c_state<=6'b101001;
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end else
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i2c_state<=6'b100101;
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end
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/****** Acknowledge (16bit) ********/
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6'b101001:begin
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SDA_direction<=0;
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SCL<=0;
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i2c_state<=6'b101010;
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end
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6'b101010:begin
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SCL<=0;
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i2c_state<=6'b101011;
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end
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6'b101011:begin
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SCL<=1;
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i2c_state<=6'b101100;
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end
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6'b101100:begin
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SCL<=1;
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if ( SDA_input==1 && DIR_latched==1'b0 ) begin
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error<=1'b1;
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end
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i2c_state<=6'b011100;
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SDA_direction<=1;
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end
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/****** separator ********/
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6'b011100:begin
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SCL<=0;
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SDA_output<=0;
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i2c_state<=6'b011101;
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end
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6'b011101:begin
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SCL<=0;
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i2c_state<=6'b011110;
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end
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6'b011110:begin
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SCL<=0;
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SDA_output<=1;
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i2c_state<=6'b011111;
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end
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6'b011111:begin
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SCL<=0;
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SDA_output<=1;
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i2c_state<=6'b100000;
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end
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6'b100000:begin
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SCL<=0;
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SDA_output<=0;
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i2c_state<=6'b100001;
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end
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/****** stop bit *******/
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6'b100001:begin
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SCL<=1;
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SDA_output<=0;
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i2c_state<=6'b100010;
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end
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6'b100010:begin
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SCL<=1;
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SDA_output<=1;
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i2c_state<=6'b100011;
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end
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6'b100011:begin
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SCL<=1;
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SDA_output<=1;
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i2c_state<=6'b100100;
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I2C_BUSY<=0;
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end
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6'b100100:begin
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if(I2C_TRANSACT==1)begin
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I2C_BUSY<=1;
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i2c_state<=0;
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data_internal<=i2c_data_write;
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address_internal<=address;
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trans_width_latch<=transact_width;
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DIR_latched<=DIR;
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error<=1'b0;
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end
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end
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default:begin
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SCL<=0;
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SDA_output<=0;
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end
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endcase
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end
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endmodule
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