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No commits in common. "e685c52ddd0099fa204182c0e962bcd90117ed9e" and "19fcf11f63c407db067d4258537b74b6d45e9572" have entirely different histories.

2 changed files with 14 additions and 17 deletions

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@ -1,4 +1,4 @@
ADD AX,#0xDEAD ADD AX,#0x55AA
ADD CX,#0xBEEF ADD CX,#0xEFBE
ADD CX,#0x4111 ADD CX,#0x1141
ADD AX,#0x2200 ADD AX,#0x1111

View File

@ -89,9 +89,6 @@ reg [15:0] temp_out;
ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C); ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
/*** Processor stages ***/ /*** Processor stages ***/
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
always @(negedge clock) begin always @(negedge clock) begin
case(state) case(state)
`PROC_IF_WRITE_CIR:begin `PROC_IF_WRITE_CIR:begin
@ -110,14 +107,13 @@ always @(negedge clock) begin
end end
`PROC_EX_STATE_EXIT:begin `PROC_EX_STATE_EXIT:begin
case(out_sel) case(out_sel)
2'b11:begin 2'b01:begin
reg_write=0; reg_write=0;
state=`PROC_IF_STATE_ENTRY;
end end
default:begin default:begin
`invalid_instruction
end end
endcase endcase
state=`PROC_IF_STATE_ENTRY;
end end
`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin `PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
external_address_bus = ProgCount; external_address_bus = ProgCount;
@ -126,6 +122,8 @@ always @(negedge clock) begin
endcase endcase
end end
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
always @(posedge clock) begin always @(posedge clock) begin
case(state) case(state)
`PROC_HALT_STATE: `PROC_HALT_STATE:
@ -153,7 +151,7 @@ always @(posedge clock) begin
unaligned_access=~unaligned_access; unaligned_access=~unaligned_access;
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=2'b11; out_sel=2'b01;
reg_read_addr=3'b000; reg_read_addr=3'b000;
reg_addr=3'b000; reg_addr=3'b000;
reg_read_read=0; reg_read_read=0;
@ -174,7 +172,7 @@ always @(posedge clock) begin
end end
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=CIR[7:6]; out_sel=2'b01;
reg_read_addr=CIR[2:0]; reg_read_addr=CIR[2:0];
reg_addr=CIR[2:0]; reg_addr=CIR[2:0];
reg_read_read=0; reg_read_read=0;
@ -198,7 +196,7 @@ always @(posedge clock) begin
end end
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=CIR[7:6]; out_sel=2'b01;
PARAM1=1; PARAM1=1;
reg_read_addr=CIR[2:0]; reg_read_addr=CIR[2:0];
reg_addr=CIR[2:0]; reg_addr=CIR[2:0];
@ -221,18 +219,17 @@ always @(posedge clock) begin
end end
`PROC_DE_LOAD_16_PARAM:begin `PROC_DE_LOAD_16_PARAM:begin
if(unaligned_access==1)begin if(unaligned_access==1)begin
PARAM1[7:0] = external_data_bus[7:0]; PARAM1[15:8] = external_data_bus[7:0];
ProgCount=ProgCount+1; ProgCount=ProgCount+1;
state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET; state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
end else begin end else begin
PARAM1[7:0] = external_data_bus[15:8]; PARAM1 <= external_data_bus;
PARAM1[15:8] = external_data_bus[7:0];
ProgCount=ProgCount+1; ProgCount=ProgCount+1;
state=`PROC_EX_STATE_ENTRY; state=`PROC_EX_STATE_ENTRY;
end end
end end
`PROC_DE_LOAD_16_EXTRA_FETCH:begin `PROC_DE_LOAD_16_EXTRA_FETCH:begin
PARAM1[15:8] = external_data_bus[15:8]; PARAM1[7:0] = external_data_bus[15:8];
state=`PROC_EX_STATE_ENTRY; state=`PROC_EX_STATE_ENTRY;
end end
`PROC_EX_STATE_ENTRY:begin `PROC_EX_STATE_ENTRY:begin