.gitignore

@@ -1,4 +0,0 @@
-*.vvp
-*.vpi
-*.lx2
-*.o

cpu/Makefile

@@ -1,21 +0,0 @@
-SOURCES=processor.v testbench.v
-VVP=processor.vvp
-
-.PHONY: run
-run: ${VVP}
-	vvp ${VVP}
-
-.PHONY: build
-build: ${VVP}
-
-.PHONY: wave
-wave: ${VVP}
-	vvp ${VVP} -lxt2
-	gtkwave test.lx2 gtkwave_savefile.gtkw
-
-${VVP} : ${SOURCES}
-	iverilog -g2012 $^ -o $@
-
-.PHONY: clean
-clean:
-	rm -f ${VVP} test.lx2

cpu/gtkwave_savefile.gtkw

@@ -1,26 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Wed Feb  8 09:34:17 2023
-[*]
-[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
-[dumpfile_mtime] "Wed Feb  8 09:33:52 2023"
-[dumpfile_size] 362
-[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
-[timestart] 0
-[size] 1630 1059
-[pos] -1 -1
-*-20.795050 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] tb.
-[sst_width] 221
-[signals_width] 214
-[sst_expanded] 1
-[sst_vpaned_height] 313
-@28
-tb.p.clock[0]
-tb.p.reset[0]
-tb.p.start[0]
-tb.p.state[1:0]
-@29
-tb.p.instruction_finished[0]
-[pattern_trace] 1
-[pattern_trace] 0

cpu/processor.v

@@ -1,90 +0,0 @@
-`timescale 1ns/1ps
-
-module clock_gen (input enable, output reg clk);
-  
-  parameter FREQ = 1000;  // in HZ
-  parameter PHASE = 0;    // in degrees
-  parameter DUTY = 50;    // in percentage 
-  
-  real clk_pd  		= 1.0/FREQ * 1000000; 	// convert to ms
-  real clk_on  		= DUTY/100.0 * clk_pd;
-  real clk_off 		= (100.0 - DUTY)/100.0 * clk_pd;
-  real quarter 		= clk_pd/4;
-  real start_dly        = quarter * PHASE/90;
-  
-  reg start_clk;
-  
-  initial begin
-  end
-  
-  // Initialize variables to zero
-  initial begin
-    clk <= 0;
-    start_clk <= 0;
-  end
-  
-  // When clock is enabled, delay driving the clock to one in order
-  // to achieve the phase effect. start_dly is configured to the 
-  // correct delay for the configured phase. When enable is 0,
-  // allow enough time to complete the current clock period
-  always @ (posedge enable or negedge enable) begin
-    if (enable) begin
-      #(start_dly) start_clk = 1;
-    end else begin
-      #(start_dly) start_clk = 0;
-    end      
-  end
-  
-  // Achieve duty cycle by a skewed clock on/off time and let this
-  // run as long as the clocks are turned on.
-  always @(posedge start_clk) begin
-    if (start_clk) begin
-      	clk = 1;
-      
-      	while (start_clk) begin
-      		#(clk_on)  clk = 0;
-    		#(clk_off) clk = 1;
-        end
-      
-      	clk = 0;
-    end
-  end 
-endmodule
-
-
-module processor ( input clock, input reset );
-  reg [1:0] state;
-  reg start=0;
-  reg instruction_finished;
-
-  /* RESET LOGIC */
-  always @(negedge reset) begin
-    if (reset==0) begin
-      @(posedge clock);
-      state=0;
-      #10
-      start=1;
-    end
-  end
-
-  /* CLOCK LOGIC */
-  always @(posedge clock) begin
-    if(instruction_finished) begin 
-      state =0;
-    end else begin
-      if (clock && start==1) begin
-        state=state+1;
-      end
-    end
-  end
-
-  always @(state) begin
-	  if (state==2) begin
-		  instruction_finished=1;
-	  end else begin
-		  instruction_finished=0;
-	  end
-  end
-
-
-endmodule

cpu/testbench.v

@@ -1,23 +0,0 @@
-module tb;
-  wire clock;
-  reg reset;
-  reg  clk_enable;
-
-  processor p(clock,reset);
-  
-  clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
-
-  initial begin
-    $dumpfile("test.lx2");
-    $dumpvars(0,p);
-    clk_enable <= 1;
-
-    #($random%500)
-    reset = 0;
-    #(100) 
-    reset = 1;
-    #(10000)
-
-    #50 $finish;
-  end
-endmodule