Standardised indentation

cpu/Makefile

@@ -1,4 +1,4 @@
-SOURCES=processor.v testbench.v
+SOURCES=processor.v testbench.v memory.v
 VVP=processor.vvp
 
 .PHONY: run

cpu/boot_code.txt

@@ -0,0 +1,17 @@
+// 0x00000000
+55AA
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000
+0000

cpu/gtkwave_savefile.gtkw

@@ -1,18 +1,18 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Wed Feb  8 09:34:17 2023
+[*] Wed Feb  8 11:44:52 2023
 [*]
 [dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
-[dumpfile_mtime] "Wed Feb  8 09:33:52 2023"
+[dumpfile_mtime] "Wed Feb  8 11:44:20 2023"
-[dumpfile_size] 362
+[dumpfile_size] 430
 [savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
 [timestart] 0
-[size] 1630 1059
+[size] 1342 1059
 [pos] -1 -1
-*-20.795050 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-20.795050 2883000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [sst_width] 221
-[signals_width] 214
+[signals_width] 293
 [sst_expanded] 1
 [sst_vpaned_height] 313
 @28
@@ -20,7 +20,11 @@ tb.p.clock[0]
 tb.p.reset[0]
 tb.p.start[0]
 tb.p.state[1:0]
-@29
 tb.p.instruction_finished[0]
+@22
+tb.p.external_address_bus[19:0]
+tb.p.external_data_bus[15:0]
+@29
+tb.p.read[0]
 [pattern_trace] 1
 [pattern_trace] 0

cpu/memory.v

@@ -0,0 +1,7 @@
+module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
+reg [15:0] memory [15:0];
+initial begin
+	$readmemh("boot_code.txt", memory);
+end
+assign data = !rd & !cs ? memory[address]: 'hz;
+endmodule

cpu/processor.v

@@ -52,16 +52,22 @@ module clock_gen (input enable, output reg clk);
 endmodule
 
 
-module processor ( input clock, input reset );
+module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
+/* State */
 reg [1:0] state;
 reg start=0;
 reg instruction_finished;
 
+/* Registers */
+reg [19:0] ProgCount;
+
+
 /* RESET LOGIC */
 always @(negedge reset) begin
 	if (reset==0) begin
 		@(posedge clock);
 		state=0;
+		ProgCount=0;//TODO: Reset Vector
 		#10
 		start=1;
 	end
@@ -86,5 +92,13 @@ module processor ( input clock, input reset );
 	end
 end
 
+/* Processor stages */
+always @(state) begin
+	if (state==0) begin
+		external_address_bus <= ProgCount;
+		read <= 0;
+		write <= 1;
+	end
+end
 
 endmodule

cpu/testbench.v

@@ -2,11 +2,17 @@ module tb;
 wire clock;
 reg reset;
 reg  clk_enable;
+wire [19:0]address_bus;
+wire [15:0]data_bus;
+wire rd,wr,romcs;
 
-  processor p(clock,reset);
+processor p(clock,reset,address_bus,data_bus,rd,wr);
+rom bootrom(address_bus,data_bus,rd,romcs);
 
 clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
 
+assign romcs=0;
+
 initial begin
 	$dumpfile("test.lx2");
 	$dumpvars(0,p);