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No commits in common. "a5571fda122c9552c6b48e6bff6f2bee0db26c5d" and "be31d74f74d864802d95b3ff3de77406c0e0f133" have entirely different histories.
a5571fda12
...
be31d74f74
@ -1,5 +1,4 @@
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SOURCES=processor.v testbench.v memory.v registers.v alu.v
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INCLUDES=proc_state_def.v
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SOURCES=processor.v testbench.v memory.v
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VVP=processor.vvp
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.PHONY: run
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@ -14,8 +13,8 @@ wave: ${VVP}
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vvp ${VVP} -lxt2
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gtkwave test.lx2 gtkwave_savefile.gtkw
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${VVP} : ${SOURCES} ${INCLUDES}
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iverilog -g2012 ${SOURCES} -o $@
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${VVP} : ${SOURCES}
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iverilog -g2012 $^ -o $@
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.PHONY: clean
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clean:
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@ -1,9 +0,0 @@
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module ADDER16(input [15:0]A,input [15:0]B, input oe,output [15:0]OUT, output carry);
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wire c;
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wire [15:0]sum;
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assign {c,sum} = A+B;
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assign OUT = !oe ? sum : 16'hz;
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assign carry = !oe ? c : 'hz;
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endmodule
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@ -1,56 +1,34 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Feb 9 20:13:04 2023
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[*] Thu Feb 9 14:44:08 2023
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[*]
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[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
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[dumpfile_mtime] "Thu Feb 9 20:10:34 2023"
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[dumpfile_size] 1043
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[dumpfile_mtime] "Thu Feb 9 14:43:59 2023"
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[dumpfile_size] 757
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[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
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[timestart] 0
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[size] 1438 1059
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[size] 1630 1059
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[pos] -1 -1
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*-22.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-22.795050 2010000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[treeopen] tb.p.
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[treeopen] tb.p.exec_units.
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[sst_width] 221
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[signals_width] 293
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[sst_expanded] 1
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[sst_vpaned_height] 313
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@28
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@29
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tb.p.clock[0]
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@28
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tb.p.reset[0]
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tb.p.state[3:0]
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@22
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tb.p.state[3:0]
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tb.p.external_address_bus[19:0]
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tb.p.external_data_bus[15:0]
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tb.p.CIR[15:0]
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@28
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tb.p.EXCEPTION[0]
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@c00022
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tb.p.exec_units.ADDER16_1.A[15:0]
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@28
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(0)tb.p.exec_units.ADDER16_1.A[15:0]
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(1)tb.p.exec_units.ADDER16_1.A[15:0]
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(2)tb.p.exec_units.ADDER16_1.A[15:0]
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(3)tb.p.exec_units.ADDER16_1.A[15:0]
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(4)tb.p.exec_units.ADDER16_1.A[15:0]
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(5)tb.p.exec_units.ADDER16_1.A[15:0]
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(6)tb.p.exec_units.ADDER16_1.A[15:0]
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(7)tb.p.exec_units.ADDER16_1.A[15:0]
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(8)tb.p.exec_units.ADDER16_1.A[15:0]
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(9)tb.p.exec_units.ADDER16_1.A[15:0]
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(10)tb.p.exec_units.ADDER16_1.A[15:0]
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(11)tb.p.exec_units.ADDER16_1.A[15:0]
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(12)tb.p.exec_units.ADDER16_1.A[15:0]
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(13)tb.p.exec_units.ADDER16_1.A[15:0]
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(14)tb.p.exec_units.ADDER16_1.A[15:0]
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(15)tb.p.exec_units.ADDER16_1.A[15:0]
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@1401200
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-group_end
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tb.p.ADD_INST[0]
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tb.p.INC_INST[0]
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@22
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tb.p.exec_units.ADDER16_1.B[15:0]
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@29
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tb.p.exec_units.register_file.write1[0]
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tb.p.PARAM1[15:0]
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[pattern_trace] 1
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[pattern_trace] 0
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@ -10,4 +10,3 @@
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/*EXECUTE STATE*/
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`define PROC_EX_STATE_ENTRY 4'b1000
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`define PROC_EX_STATE_EXIT 4'b1001
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@ -1,38 +1,6 @@
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`include "proc_state_def.v"
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module exec_units ( input [15:0]PARAM1, input [15:0]PARAM2, input [1:0]in1_sel, input [1:0]in2_sel, input [1:0]out_sel , input EXEC);
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/*Architectural Register file*/
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wire [2:0] reg_addr;
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wire [15:0] reg_data;
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wire reg_read;
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wire reg_write;
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wire [2:0] reg_read_addr;
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wire [15:0] reg_read_data;
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wire reg_read_read;
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register_file register_file(reg_addr,reg_data,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);
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/*Exec Unts*/
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,EXEC,ADDER16_1O,ADDER16_1C);
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/*logic*/
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assign reg_addr=PARAM2[5:3];
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assign reg_read=EXEC;
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assign reg_write=EXEC;
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assign reg_read_read=0;
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assign reg_read_addr=PARAM2[2:0];
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assign ADDER16_1A= (in1_sel==2'b00) ? PARAM1 : 16'b1010101010101010;
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assign ADDER16_1B= (in2_sel==2'b01) ? reg_read_data : 16'b1010101010101010;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : 'hz;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : ADDER16_1O;
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assign reg_data = ADDER16_1O;
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endmodule
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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/* State */
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reg [3:0] state;
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reg instruction_finished;
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@ -43,30 +11,24 @@ reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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/* Execution units*/
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reg [1:0] in1_sel;
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reg [1:0] in2_sel;
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reg [1:0] out_sel;
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reg exec_unit_execute;
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exec_units exec_units(PARAM1,PARAM2,in1_sel,in2_sel,out_sel,exec_unit_execute);
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/* RESET LOGIC */
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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ProgCount=0;//TODO: Reset Vector
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ADD_INST=0;
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EXCEPTION=0;
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INC_INST=0;
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HALT=0;
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exec_unit_execute=1;
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@(negedge clock);
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@(posedge clock);
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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reg EXCEPTION;
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/* Processor stages */
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reg ADD_INST,EXCEPTION,INC_INST;
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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@ -74,21 +36,14 @@ always @(negedge clock) begin
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ProgCount=ProgCount+1;
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state=`PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_EXIT:begin
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exec_unit_execute=1;
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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end
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:
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HALT=1;
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`PROC_IF_STATE_ENTRY:begin
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EXCEPTION=0;
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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@ -98,46 +53,37 @@ always @(posedge clock) begin
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external_address_bus <= ProgCount; /*Remenance from IF*/
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case(CIR[15:10])
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6'b100000 : begin
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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case (CIR[5:3])
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3'b000 :begin
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/* Add Immediate to register/memory */
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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ADD_INST=1;
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state=`PROC_DE_LOAD_16_PARAM;
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end
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default:begin
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`invalid_instruction
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000 :begin
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/* Increment Register or Memmory */
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM1=1;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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INC_INST=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end else begin
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`invalid_instruction
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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default:begin
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`invalid_instruction
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end
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@ -147,9 +93,8 @@ always @(posedge clock) begin
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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EXCEPTION=0;
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exec_unit_execute=0;
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state=`PROC_EX_STATE_EXIT;
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EXCEPTION=0;ADD_INST=0;INC_INST=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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end
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@ -1,21 +0,0 @@
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module register_file ( input [2:0]addr1, inout [15:0]data1, input wire read1, input wire write1 ,input [2:0]addr2,output [15:0]data2,input wire read2);
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reg [15:0] registers [7:0];
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assign data2 = !read2 ? registers[0] : 'b1111000011110000 ;
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//assign data2 = !read2 ? registers[addr2]: 'b1111000011110000;
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assign data1 = !read1 ? registers[addr1]: 'hz;
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initial begin
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registers['b000]=0;
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registers['b001]=0;
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registers['b010]=0;
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registers['b011]=0;
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registers['b100]=0;
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registers['b101]=0;
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registers['b110]=0;
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registers['b111]=0; // TODO Don't clear. Remove after we implement the MOV instruction
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end
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always @(negedge write1) begin
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registers[addr1] = data1;
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//$display("registers: 0:%04x 1:%04x 2:%04x",registers[0],registers[1],registers[2]);
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$display("register %d update to %04x (data bus %04x)",addr1,registers[addr1],data1);
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end
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endmodule
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@ -27,7 +27,6 @@ initial begin
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#(`CPU_SPEED)
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reset = 1;
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#(`CPU_SPEED*30)
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//$writememh("register_dump.txt", registers);
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#50 $finish;
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end
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