Fixed bug introduced in a previous commit about fixing ADD

system/decoder.v

@@ -100,19 +100,17 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 				reg_read_port2_addr={Wbit,3'b000};
 				reg_write_addr={Wbit,3'b000};
 				ALU_1OP=`ALU_OP_ADD;
-				case({Sbit,Wbit})
-					2'b00,2'b11:
-						next_state=`PROC_DE_LOAD_8_PARAM;
-					2'b01:
+				if(Wbit)
 					next_state=`PROC_DE_LOAD_16_PARAM;
-					default:begin
-						`invalid_instruction
+				else
+					next_state=`PROC_DE_LOAD_8_PARAM;
 			end
-				endcase
-			end
-			11'b1000_00xx_000 : begin
+			11'b1000_00xx_101, /* SUB */
+				11'b1000_00xx_000 : /* ADD */ begin
 				/*                                  ADD - Add Immediate word/byte to register/memory                                      */
 				/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
+				/*                                  SUB - Subtract mmediate word/byte from register/memory                                */
+				/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
 				opcode_size=1;
 				has_operands=1;
 				Wbit=CIR[8:8];
@@ -124,7 +122,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 				OUT_MOD={1'b0,IN_MOD};
 				reg_read_port2_addr={Wbit,RM};
 				reg_write_addr={Wbit,RM};
-				ALU_1OP=`ALU_OP_ADD;
 				case({Sbit,Wbit})
 					2'b00,2'b11:begin
 						`start_unaligning_instruction
@@ -138,6 +135,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 						`invalid_instruction
 					end
 				endcase
+				case(CIR[5:3])
+					3'b000: ALU_1OP=`ALU_OP_ADD;
+					3'b101: ALU_1OP=`ALU_OP_SUB_REVERSE;
+					default:begin
+						/*Should be impossible*/
+						`invalid_instruction
+					end
+				endcase
 			end
 			11'b1000_00xx_111 : begin
 				/*                                  CMP - compare Immediate with register / memory                                        */