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2 Commits
19fcf11f63
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e685c52ddd
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e685c52ddd | |||
6561018206 |
@ -1,4 +1,4 @@
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ADD AX,#0x55AA
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ADD AX,#0xDEAD
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ADD CX,#0xEFBE
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ADD CX,#0xBEEF
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ADD CX,#0x1141
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ADD CX,#0x4111
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ADD AX,#0x1111
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ADD AX,#0x2200
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@ -89,6 +89,9 @@ reg [15:0] temp_out;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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/*** Processor stages ***/
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/*** Processor stages ***/
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
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always @(negedge clock) begin
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always @(negedge clock) begin
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case(state)
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case(state)
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`PROC_IF_WRITE_CIR:begin
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`PROC_IF_WRITE_CIR:begin
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@ -107,13 +110,14 @@ always @(negedge clock) begin
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end
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end
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`PROC_EX_STATE_EXIT:begin
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`PROC_EX_STATE_EXIT:begin
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case(out_sel)
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case(out_sel)
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2'b01:begin
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2'b11:begin
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reg_write=0;
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reg_write=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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default:begin
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default:begin
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`invalid_instruction
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end
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end
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endcase
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endcase
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
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`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
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external_address_bus = ProgCount;
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external_address_bus = ProgCount;
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@ -122,8 +126,6 @@ always @(negedge clock) begin
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endcase
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endcase
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end
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end
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
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always @(posedge clock) begin
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always @(posedge clock) begin
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case(state)
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case(state)
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`PROC_HALT_STATE:
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`PROC_HALT_STATE:
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@ -151,7 +153,7 @@ always @(posedge clock) begin
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unaligned_access=~unaligned_access;
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unaligned_access=~unaligned_access;
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in1_sel=2'b00;
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in1_sel=2'b00;
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in2_sel=2'b01;
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in2_sel=2'b01;
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out_sel=2'b01;
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out_sel=2'b11;
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reg_read_addr=3'b000;
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reg_read_addr=3'b000;
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reg_addr=3'b000;
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reg_addr=3'b000;
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reg_read_read=0;
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reg_read_read=0;
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@ -172,7 +174,7 @@ always @(posedge clock) begin
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end
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end
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in1_sel=2'b00;
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in1_sel=2'b00;
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in2_sel=2'b01;
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in2_sel=2'b01;
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out_sel=2'b01;
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out_sel=CIR[7:6];
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reg_read_addr=CIR[2:0];
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reg_read_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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reg_read_read=0;
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reg_read_read=0;
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@ -196,7 +198,7 @@ always @(posedge clock) begin
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end
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end
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in1_sel=2'b00;
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in1_sel=2'b00;
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in2_sel=2'b01;
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in2_sel=2'b01;
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out_sel=2'b01;
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out_sel=CIR[7:6];
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PARAM1=1;
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PARAM1=1;
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reg_read_addr=CIR[2:0];
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reg_read_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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@ -219,17 +221,18 @@ always @(posedge clock) begin
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end
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end
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`PROC_DE_LOAD_16_PARAM:begin
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`PROC_DE_LOAD_16_PARAM:begin
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if(unaligned_access==1)begin
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if(unaligned_access==1)begin
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PARAM1[15:8] = external_data_bus[7:0];
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PARAM1[7:0] = external_data_bus[7:0];
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ProgCount=ProgCount+1;
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ProgCount=ProgCount+1;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
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end else begin
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end else begin
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PARAM1 <= external_data_bus;
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PARAM1[7:0] = external_data_bus[15:8];
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PARAM1[15:8] = external_data_bus[7:0];
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ProgCount=ProgCount+1;
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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end
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH:begin
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`PROC_DE_LOAD_16_EXTRA_FETCH:begin
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PARAM1[7:0] = external_data_bus[15:8];
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PARAM1[15:8] = external_data_bus[15:8];
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state=`PROC_EX_STATE_ENTRY;
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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`PROC_EX_STATE_ENTRY:begin
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`PROC_EX_STATE_ENTRY:begin
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