cpu/Makefile

@@ -1,4 +1,4 @@
-SOURCES=processor.v testbench.v memory.v
+SOURCES=processor.v testbench.v
 VVP=processor.vvp
 
 .PHONY: run

cpu/boot_code.txt

@@ -1,17 +0,0 @@
-// 0x00000000
-55AA
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000
-0000

cpu/gtkwave_savefile.gtkw

@@ -1,18 +1,18 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Wed Feb  8 11:44:52 2023
+[*] Wed Feb  8 09:34:17 2023
 [*]
 [dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
-[dumpfile_mtime] "Wed Feb  8 11:44:20 2023"
+[dumpfile_mtime] "Wed Feb  8 09:33:52 2023"
-[dumpfile_size] 430
+[dumpfile_size] 362
 [savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
 [timestart] 0
-[size] 1342 1059
+[size] 1630 1059
 [pos] -1 -1
-*-20.795050 2883000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-20.795050 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [sst_width] 221
-[signals_width] 293
+[signals_width] 214
 [sst_expanded] 1
 [sst_vpaned_height] 313
 @28
@@ -20,11 +20,7 @@ tb.p.clock[0]
 tb.p.reset[0]
 tb.p.start[0]
 tb.p.state[1:0]
-tb.p.instruction_finished[0]
-@22
-tb.p.external_address_bus[19:0]
-tb.p.external_data_bus[15:0]
 @29
-tb.p.read[0]
+tb.p.instruction_finished[0]
 [pattern_trace] 1
 [pattern_trace] 0

cpu/memory.v

@@ -1,7 +0,0 @@
-module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
-reg [15:0] memory [15:0];
-initial begin
-	$readmemh("boot_code.txt", memory);
-end
-assign data = !rd & !cs ? memory[address]: 'hz;
-endmodule

cpu/processor.v

@@ -2,42 +2,42 @@
 
 module clock_gen (input enable, output reg clk);
   
-parameter FREQ = 1000;  // in HZ
+  parameter FREQ = 1000;  // in HZ
-parameter PHASE = 0;    // in degrees
+  parameter PHASE = 0;    // in degrees
-parameter DUTY = 50;    // in percentage 
+  parameter DUTY = 50;    // in percentage 
   
-real clk_pd	= 1.0/FREQ * 1000000; 	// convert to ms
+  real clk_pd  		= 1.0/FREQ * 1000000; 	// convert to ms
-real clk_on	= DUTY/100.0 * clk_pd;
+  real clk_on  		= DUTY/100.0 * clk_pd;
-real clk_off	= (100.0 - DUTY)/100.0 * clk_pd;
+  real clk_off 		= (100.0 - DUTY)/100.0 * clk_pd;
-real quarter	= clk_pd/4;
+  real quarter 		= clk_pd/4;
-real start_dly	= quarter * PHASE/90;
+  real start_dly        = quarter * PHASE/90;
   
-reg start_clk;
+  reg start_clk;
   
-initial begin
+  initial begin
-end
+  end
   
-// Initialize variables to zero
+  // Initialize variables to zero
-initial begin
+  initial begin
     clk <= 0;
     start_clk <= 0;
-end
+  end
   
-// When clock is enabled, delay driving the clock to one in order
+  // When clock is enabled, delay driving the clock to one in order
-// to achieve the phase effect. start_dly is configured to the 
+  // to achieve the phase effect. start_dly is configured to the 
-// correct delay for the configured phase. When enable is 0,
+  // correct delay for the configured phase. When enable is 0,
-// allow enough time to complete the current clock period
+  // allow enough time to complete the current clock period
-always @ (posedge enable or negedge enable) begin
+  always @ (posedge enable or negedge enable) begin
     if (enable) begin
       #(start_dly) start_clk = 1;
     end else begin
       #(start_dly) start_clk = 0;
     end      
-end
+  end
   
-// Achieve duty cycle by a skewed clock on/off time and let this
+  // Achieve duty cycle by a skewed clock on/off time and let this
-// run as long as the clocks are turned on.
+  // run as long as the clocks are turned on.
-always @(posedge start_clk) begin
+  always @(posedge start_clk) begin
     if (start_clk) begin
       	clk = 1;
       
@@ -48,33 +48,27 @@ always @(posedge start_clk) begin
       
       	clk = 0;
     end
-end 
+  end 
 endmodule
 
 
-module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
+module processor ( input clock, input reset );
-/* State */
+  reg [1:0] state;
-reg [1:0] state;
+  reg start=0;
-reg start=0;
+  reg instruction_finished;
-reg instruction_finished;
 
-/* Registers */
+  /* RESET LOGIC */
-reg [19:0] ProgCount;
+  always @(negedge reset) begin
-
-
-/* RESET LOGIC */
-always @(negedge reset) begin
     if (reset==0) begin
       @(posedge clock);
       state=0;
-		ProgCount=0;//TODO: Reset Vector
       #10
       start=1;
     end
-end
+  end
 
-/* CLOCK LOGIC */
+  /* CLOCK LOGIC */
-always @(posedge clock) begin
+  always @(posedge clock) begin
     if(instruction_finished) begin 
       state =0;
     end else begin
@@ -82,23 +76,15 @@ always @(posedge clock) begin
         state=state+1;
       end
     end
-end
+  end
 
-always @(state) begin
+  always @(state) begin
 	  if (state==2) begin
 		  instruction_finished=1;
 	  end else begin
 		  instruction_finished=0;
 	  end
-end
-
-/* Processor stages */
-always @(state) begin
-	if (state==0) begin
-		external_address_bus <= ProgCount;
-		read <= 0;
-		write <= 1;
   end
-end
+
 
 endmodule

cpu/testbench.v

@@ -1,19 +1,13 @@
 module tb;
-wire clock;
+  wire clock;
-reg reset;
+  reg reset;
-reg  clk_enable;
+  reg  clk_enable;
-wire [19:0]address_bus;
-wire [15:0]data_bus;
-wire rd,wr,romcs;
 
-processor p(clock,reset,address_bus,data_bus,rd,wr);
+  processor p(clock,reset);
-rom bootrom(address_bus,data_bus,rd,romcs);
   
-clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
+  clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
 
-assign romcs=0;
+  initial begin
-
-initial begin
     $dumpfile("test.lx2");
     $dumpvars(0,p);
     clk_enable <= 1;
@@ -25,5 +19,5 @@ initial begin
     #(10000)
 
     #50 $finish;
-end
+  end
 endmodule