Made execute unit run in parallel with everything else. Still not parallel for most of the time though
This commit is contained in:
parent
7151d5634f
commit
fe0426a77b
@ -10,7 +10,7 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
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* [X] Is Turing complete
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* [ ] Can boot up MS-DOS / FreeDOS
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* [ ] Is completely binary compatible
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* [ ] Is pipelined
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* [X] Is pipelined
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* [ ] Is Out of Order
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* [ ] Is superscalar
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* [ ] Has been successfully synthesized
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@ -1,42 +1,63 @@
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[*]
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[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
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[*] Thu May 11 08:14:36 2023
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[*] Sat May 13 03:32:49 2023
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[*]
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[dumpfile] "/home/user/9086/system/boot_code.fst"
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[dumpfile_mtime] "Thu May 11 08:13:23 2023"
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[dumpfile_size] 2215158
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[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
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[timestart] 29810000000
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[size] 1236 993
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[dumpfile] "/home/user/9086_take_two/system/boot_code.fst"
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[dumpfile_mtime] "Sat May 13 03:30:49 2023"
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[dumpfile_size] 8561
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[savefile] "/home/user/9086_take_two/gtkwave_savefile.gtkw"
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[timestart] 102870000000
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[size] 1140 993
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[pos] -1 -1
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*-31.895050 34640000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-33.395050 121840000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.system.
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[treeopen] TOP.system.p.
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[treeopen] TOP.system.p.BIU.
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[treeopen] TOP.system.p.decoder.
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[treeopen] TOP.system.p.execute_unit.
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[sst_width] 263
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[signals_width] 293
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[signals_width] 231
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[sst_expanded] 1
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[sst_vpaned_height] 295
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[sst_vpaned_height] 296
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@28
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TOP.system.clock
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TOP.system.reset
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@22
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TOP.system.address_bus[19:0]
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TOP.system.data_bus[15:0]
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TOP.system.p.BIU.biu_state[3:0]
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@28
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TOP.system.p.read
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TOP.system.p.write
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TOP.system.IOMEM
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@200
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-
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@28
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TOP.system.p.BIU.VALID_INSTRUCTION
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TOP.system.p.valid_exec_data
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@22
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TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
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TOP.system.p.BIU.biu_state[3:0]
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@28
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.BIU.write_request
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@29
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TOP.system.p.BIU.read_request
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@28
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TOP.system.p.SIMPLE_MICRO
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@22
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TOP.system.p.ucode_seq_addr[4:0]
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@28
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TOP.system.p.execute_unit.biu_jump_req
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TOP.system.p.execute_unit.stall
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@200
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-
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@28
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TOP.system.p.ERROR[2:0]
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TOP.system.IOMEM
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TOP.system.p.HALT
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@22
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TOP.system.p.BIU.INSTRUCTION[31:0]
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@28
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TOP.system.p.BIU.VALID_INSTRUCTION
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@22
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TOP.system.p.decoder.seq_addr_entry[4:0]
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TOP.system.p.BIU.FIFO_end[3:0]
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TOP.system.p.BIU.FIFO_start[3:0]
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TOP.system.p.BIU.INPUT_FIFO[0][7:0]
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@ -55,13 +76,5 @@ TOP.system.p.BIU.INPUT_FIFO[12][7:0]
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TOP.system.p.BIU.INPUT_FIFO[13][7:0]
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TOP.system.p.BIU.INPUT_FIFO[14][7:0]
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TOP.system.p.BIU.INPUT_FIFO[15][7:0]
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TOP.system.p.ucode_seq_addr[4:0]
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@28
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.state[2:0]
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TOP.system.p.valid_exec_data
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TOP.system.p.reg_write_we
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@29
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TOP.system.p.SIMPLE_MICRO
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[pattern_trace] 1
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[pattern_trace] 0
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41
system/biu.v
41
system/biu.v
@ -42,7 +42,7 @@ module BIU (
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/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
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/* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req,
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/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
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/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO
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/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO,input stall
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);
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reg [15:0] data_bus_output_register;
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@ -63,6 +63,7 @@ reg [3:0] biu_state;
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always @(negedge reset) begin
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biu_state <= `BIU_HALT;
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write <= 1;
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end
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always @(posedge reset) begin
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biu_state <= `BIU_RESET;
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@ -120,24 +121,26 @@ always @(posedge clock) begin
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end
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end
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if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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end else if(FIFO_SIZE>3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
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if ( !stall ) begin
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if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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end else if(FIFO_SIZE>3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
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end
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end
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end
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@ -20,7 +20,7 @@
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module execute_unit (
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/* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input
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/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/
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/* */ ,input set_initial_values
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/* */ ,input set_initial_values,output stall
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/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT
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/* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state
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/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
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@ -29,6 +29,8 @@ module execute_unit (
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/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req
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);
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assign stall = work&valid_input;
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assign _exec_state_ = exec_state;
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assign _ALU_O_ = ALU_O;
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@ -70,7 +72,10 @@ ALU ALU1(
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/*############ Execute logic ########################################################## */
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always @(posedge valid_input) begin
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exec_state <= init_state;
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if(work == 0)begin
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exec_state <= init_state;
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work <= 1;
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end
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end
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always @(negedge set_initial_values) begin
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@ -87,9 +92,12 @@ always @(posedge reset) begin
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end
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`define unimpl_addressing_mode exec_state <= `EXEC_DONE;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
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reg work;
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always @(posedge clock) begin
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case (exec_state)
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`EXEC_RESET: begin
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work <= 0;
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biu_write_request <= 0;
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biu_read_request <= 0;
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biu_data_direction <= 0;
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@ -99,11 +107,13 @@ always @(posedge clock) begin
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ERROR <= `ERR_NO_ERROR;
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end
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`EXEC_DONE:begin
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work <= 0;
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reg_write_we <= 1;
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biu_jump_req <= 0;
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use_exec_reg_addr <= 0;
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end
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`EXEC_DE_LOAD_REG_TO_PARAM:begin
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work <= 1;
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PARAM2<=reg_read_port2_data;
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case(IN_MOD)
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3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
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@ -111,6 +121,7 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_DE_LOAD_8_PARAM:begin
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work <= 1;
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if(opcode_size==0)begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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@ -136,6 +147,7 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_DE_LOAD_16_PARAM:begin
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work <= 1;
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if(opcode_size==0)begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
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PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8];
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@ -149,6 +161,7 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_MEMIO_READ:begin
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work <= 1;
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/*Decode MOD R/M, read the data and place it to PARAM1*/
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case (IN_MOD)
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3'b000,
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@ -210,6 +223,7 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_MEMIO_READ_SETADDR:begin
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work <= 1;
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if(memio_address_select==0)
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BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
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else
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@ -226,10 +240,12 @@ always @(posedge clock) begin
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end
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end
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`EXEC_NEXT_INSTRUCTION:begin
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work <= 1;
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/*necessary for biu to see we went on another state from decode to give us a new instruction*/
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exec_state <= `EXEC_DONE;
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end
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`EXEC_WRITE_ENTRY:begin
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work <= 1;
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FLAGS[7:0] <= ALU_FLAGS[7:0];
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case(OUT_MOD)
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3'b000,
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@ -306,6 +322,7 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_MEMIO_WRITE:begin
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work <= 1;
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/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
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/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
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@ -72,10 +72,11 @@ assign OUT_MOD=DE_OUTPUT_sampled[49:47];
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wire [`ALU_OP_BITS-1:0] ALU_OP;
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assign ALU_OP = DE_OUTPUT_sampled[42:40];
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wire stall;
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execute_unit execute_unit (
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/* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
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/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
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/* */ ,set_initial_values
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/* */ ,set_initial_values,stall
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/* PARAM */ ,PARAM1_INIT,PARAM2_INIT
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/* STATE CONTROL */ ,exec_state, next_state
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
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@ -97,8 +98,9 @@ BIU BIU(
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/* */ ,external_data_bus,read,write,BHE,IOMEM
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/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
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/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
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/* */ ,state,SIMPLE_MICRO
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/* */ ,state,SIMPLE_MICRO,stall
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);
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assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
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/*############ Decoder ########################################################## */
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@ -193,34 +195,34 @@ always @(posedge clock) begin
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state <= `PROC_DE_STATE_ENTRY;
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end
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`PROC_DE_STATE_ENTRY:begin
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if(VALID_INSTRUCTION==1) begin
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if (!stall) begin
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if(VALID_INSTRUCTION==1) begin
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DE_OUTPUT_sampled <= DE_OUTPUT;
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DE_OUTPUT_sampled <= DE_OUTPUT;
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if(SIMPLE_MICRO==0)begin
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set_initial_values<=0;
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if(SIMPLE_MICRO==0)begin
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set_initial_values<=0;
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`ifdef DEBUG_PC_ADDRESS
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$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
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`endif
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ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
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INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
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end
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/*switch to microcode decoding*/
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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end else begin
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valid_exec_data <= 1;
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state <= `PROC_WAIT;
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`ifdef DEBUG_PC_ADDRESS
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$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
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`endif
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ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
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INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
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end
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/*switch to microcode decoding*/
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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end else begin
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valid_exec_data <= 1;
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state <= `PROC_WAIT;
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end
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end
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end
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end
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`PROC_WAIT:begin
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set_initial_values<=1;
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if( exec_state == `EXEC_DONE ) begin
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FLAGS <= {8'b0,EXEC_FLAGS}; //TODO: don't set all of them all the time!
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if(!stall) begin
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set_initial_values<=1;
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valid_exec_data<=0;
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state <= `PROC_DE_STATE_ENTRY;
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if( SIMPLE_MICRO == 1 ) begin
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@ -239,4 +241,9 @@ always @(posedge clock) begin
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endcase
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end
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always @(exec_state) begin
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if(exec_state == `EXEC_DONE)
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FLAGS <= {8'b0,EXEC_FLAGS}; //TODO: don't set all of them all the time!
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end
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endmodule
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