Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing
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@ -5,3 +5,4 @@
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*.swp
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cpu/boot_code.bin
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cpu/boot_code.txt
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cpu/memdump.txt
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@ -5,3 +5,4 @@ ADD AX,#0xDEAD
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ADD CX,#0xBEEF
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ADD CX,#0x4111
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ADD AX,#0x2200
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HLT
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@ -33,6 +33,7 @@ reg [1:0] out_sel;
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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state=`PROC_HALT_STATE;
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ProgCount=0;//TODO: Reset Vector
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EXCEPTION=0;
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HALT=0;
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@ -41,8 +42,8 @@ always @(negedge reset) begin
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reg_read_read=1;
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unaligned_access=0;
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ALU_OUT=1;
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@(posedge reset)
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@(negedge clock);
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@(posedge clock);
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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@ -128,8 +129,8 @@ end
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:
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HALT=1;
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`PROC_HALT_STATE:begin
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end
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`PROC_IF_STATE_ENTRY:begin
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EXCEPTION=0;
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external_address_bus <= ProgCount;
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@ -228,6 +229,21 @@ always @(posedge clock) begin
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`invalid_instruction
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end
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end
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6'b111101 : begin
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/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
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case (CIR[9:8])
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2'b00:begin
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/* HLT*/
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unaligned_access=~unaligned_access;
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HALT=1;
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state=`PROC_HALT_STATE;
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end
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default:begin
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`invalid_instruction;
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end
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endcase
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end
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default:begin
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`invalid_instruction
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end
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@ -16,21 +16,31 @@ rom bootrom(address_bus,data_bus,rd,romcs);
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clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
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assign romcs=0;
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integer cycles=0;
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initial begin
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$dumpfile("test.lx2");
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$dumpvars(0,p);
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reset = 0;
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clk_enable <= 1;
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#($random%500)
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reset = 0;
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#(`CPU_SPEED)
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reset = 1;
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#(`CPU_SPEED*55)
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//$writememh("register_dump.txt", registers);
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#50 $finish;
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end
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always @(posedge HALT) begin
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$display("Processor halted.\nCycles run for: %d",cycles);
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$writememh("memdump.txt", bootrom.memory);
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#(`CPU_SPEED) //Just for the waveform
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$finish;
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end
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always @(posedge clock)begin
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if(reset==1)
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cycles=cycles+1;
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end
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endmodule
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