Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing

.gitignore

@@ -5,3 +5,4 @@
 *.swp
 cpu/boot_code.bin
 cpu/boot_code.txt
+cpu/memdump.txt

cpu/boot_code.asm

@@ -5,3 +5,4 @@ ADD AX,#0xDEAD
 ADD CX,#0xBEEF
 ADD CX,#0x4111
 ADD AX,#0x2200
+HLT

cpu/processor.v

@@ -33,6 +33,7 @@ reg [1:0] out_sel;
 always @(negedge reset) begin
 	if (reset==0) begin
 		@(posedge clock);
+		state=`PROC_HALT_STATE;
 		ProgCount=0;//TODO: Reset Vector
 		EXCEPTION=0;
 		HALT=0;
@@ -41,8 +42,8 @@ always @(negedge reset) begin
 		reg_read_read=1;
 		unaligned_access=0;
 		ALU_OUT=1;
+		@(posedge reset)
 		@(negedge clock);
-		@(posedge clock);
 		state=`PROC_IF_STATE_ENTRY;
 	end
 end
@@ -128,8 +129,8 @@ end
 
 always @(posedge clock) begin
 	case(state)
-		`PROC_HALT_STATE:
+		`PROC_HALT_STATE:begin
-			HALT=1;
+		end
 		`PROC_IF_STATE_ENTRY:begin
 			EXCEPTION=0;
 			external_address_bus <= ProgCount;
@@ -228,6 +229,21 @@ always @(posedge clock) begin
 						`invalid_instruction
 					end
 				end
+				6'b111101 : begin
+					/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
+					case (CIR[9:8])
+						2'b00:begin
+							/* HLT*/
+							unaligned_access=~unaligned_access;
+							HALT=1;
+							state=`PROC_HALT_STATE;
+						end
+						default:begin
+							`invalid_instruction;
+						end
+					endcase
+
+				end
 				default:begin
 					`invalid_instruction
 				end

cpu/testbench.v

@@ -16,21 +16,31 @@ rom bootrom(address_bus,data_bus,rd,romcs);
 clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
 
 assign romcs=0;
+integer cycles=0;
 
 initial begin
 	$dumpfile("test.lx2");
 	$dumpvars(0,p);
+	reset = 0;
 	clk_enable <= 1;
 
 	#($random%500)
-	reset = 0;
 	#(`CPU_SPEED) 
 	reset = 1;
-	#(`CPU_SPEED*55)
-	//$writememh("register_dump.txt", registers);
-
-	#50 $finish;
 end
+
+always @(posedge HALT) begin
+	$display("Processor halted.\nCycles run for: %d",cycles);
+	$writememh("memdump.txt", bootrom.memory);
+	#(`CPU_SPEED) //Just for the waveform
+	$finish;
+end
+
+always @(posedge clock)begin
+	if(reset==1)
+		cycles=cycles+1;
+end
+
 endmodule