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Removed useless state in the state machine and ran the project through aspell

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-26 02:46:43 +00:00
parent 0c36e9d78c
commit f7d76f1944
3 changed files with 83 additions and 86 deletions
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6
system/decoder.v
View File

@ -109,7 +109,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
11'b1000_00xx_000 : /* ADD */ begin
/* ADD - Add Immediate word/byte to register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
/* SUB - Subtract mmediate word/byte from register/memory */
/* SUB - Subtract immediate word/byte from register/memory */
/* 1 0 0 0 0 0 S W | MOD 1 0 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
opcode_size=1;
has_operands=1;
@ -433,7 +433,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
has_operands=1;
Wbit=1;
Sbit=1;
PARAM2=2; //substract from sp
PARAM2=2; //subtract from sp
seq_addr_entry=`UCODE_CALL_ENTRY;
end
11'b1100_0011_xxx:begin
@ -580,7 +580,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
in_alu1_sel1 =ucode_data[13:12];
in_alu1_sel2 =ucode_data[15:14];
OUT_MOD =ucode_data[18:16];
/*1:1 map essentially but I want to keep the spec for these bits seperate
/*1:1 map essentially but I want to keep the spec for these bits separate
* from the alu op select bits*/
case(ucode_data[21:19])
3'b000: ALU_1OP=`ALU_OP_ADD;

161
system/processor.v
View File

@ -179,85 +179,6 @@ always @(negedge clock) begin
CIR[7:0] <= external_data_bus[15:8];
state=`PROC_DE_STATE_ENTRY;
end
`PROC_EX_STATE_EXIT:begin
/*Don't update the unaligned_access for Instruction
* Fetch if we are doing microcode execution, it will
* be done by decode at the end*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
unaligned_access=unaligning_instruction^unaligned_access;
case(OUT_MOD)
3'b000,
3'b001,
3'b010 : begin
case (RM) /* Duplicate code with write... */
3'b000:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b001:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b010:begin
/*[BP]+[SI]*/
`invalid_instruction
end
3'b011:begin
/*[BP]+[DI]*/
`invalid_instruction
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr=4'b1110;
state=`PROC_MEMIO_WRITE;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr=4'b1111;
state=`PROC_MEMIO_WRITE;
end
3'b110:begin
/*d16 */
`invalid_instruction
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr=4'b1011;
state=`PROC_MEMIO_WRITE;
end
endcase
end
3'b011:begin
reg_write_we=0;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b100:begin /*No output*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b101:begin /* Program Counter*/
ProgCount={5'b00000,ALU_1O[15:1]};
unaligned_access=ALU_1O[0:0];
we_jumped=1;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b110:begin /* SP Indirect write*/
reg_read_port1_addr=4'b1100;
state=`PROC_MEMIO_WRITE;
end
default:begin
`invalid_instruction
end
endcase
end
`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
external_address_bus = ProgCount;
state=`PROC_DE_LOAD_16_EXTRA_FETCH;
@ -345,7 +266,7 @@ always @(posedge clock) begin
`PROC_DE_STATE_ENTRY:begin
/* If we are unaligned, the address bus contains the
* ProgCount and points to the second word containing
* the nest unread byte in extenral_data_bus[7:0]. If
* the next unread byte in external_data_bus[7:0]. If
* we are aligned the address bus points to the first
* word of the instruction which contains no useful
* data anymore but the ProgCount has the correct
@ -355,7 +276,7 @@ always @(posedge clock) begin
external_address_bus = ProgCount;
if(SIMPLE_MICRO==0)begin
/* We cannot set these directly within
* microcode so don't overwirte useful values
* microcode so don't overwrite useful values
* each time the next microcode is executed.
* Note this still allows to set initial values
* at the start of the microcode */
@ -517,7 +438,83 @@ always @(posedge clock) begin
end
`PROC_EX_STATE_ENTRY:begin
FLAGS[7:0] = ALU_1FLAGS[7:0]; //TODO, we should probably move all the ...STATE_EXIT stuff here
state=`PROC_EX_STATE_EXIT;
/*Don't update the unaligned_access for Instruction
* Fetch if we are doing microcode execution, it will
* be done by decode at the end*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
unaligned_access=unaligning_instruction^unaligned_access;
case(OUT_MOD)
3'b000,
3'b001,
3'b010 : begin
case (RM) /* Duplicate code with write... */
3'b000:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b001:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b010:begin
/*[BP]+[SI]*/
`invalid_instruction
end
3'b011:begin
/*[BP]+[DI]*/
`invalid_instruction
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr=4'b1110;
state=`PROC_MEMIO_WRITE;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr=4'b1111;
state=`PROC_MEMIO_WRITE;
end
3'b110:begin
/*d16 */
`invalid_instruction
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr=4'b1011;
state=`PROC_MEMIO_WRITE;
end
endcase
end
3'b011:begin
reg_write_we=0;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b100:begin /*No output*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b101:begin /* Program Counter*/
ProgCount={5'b00000,ALU_1O[15:1]};
unaligned_access=ALU_1O[0:0];
we_jumped=1;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b110:begin /* SP Indirect write*/
reg_read_port1_addr=4'b1100;
state=`PROC_MEMIO_WRITE;
end
default:begin
`invalid_instruction
end
endcase
end
`PROC_MEMIO_WRITE:begin
/* ADDRESS: reg_read_port1_data DATA:ALU1_O */

2
system/ucode.txt
View File

@ -1,4 +1,4 @@
/* ucode.txt - The contents of the microcode rom for the 9086 cpu
/* ucode.txt - The contents of the microcode rom for the 9086 CPU
This file is part of the 9086 project.