Cleaned up some pieces of code and fixed a bug

system/decoder.v

@@ -76,8 +76,6 @@ wire [`UCODE_DATA_BITS-1:0] ucode_data;
 
 microcode ucode(seq_addr_input,ucode_data);
 
-/* 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 */
-
 `define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR<=1;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
 
 
@@ -648,7 +646,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 			3'b100: next_state=`PROC_MEMIO_READ_SETADDR;
 			default: begin end /*impossible*/
 		endcase
-		if(ucode_data[36:36]==0)
+		if(ucode_data[36:36]==0) /*Set reg write address*/
 			reg_write_addr = ucode_data[12:9 ];
 		in_alu1_sel1  = ucode_data[14:13];
 		in_alu1_sel2  = ucode_data[16:15];
@@ -666,13 +664,13 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 			3'b111: ALU_1OP=`ALU_OP_SHIFT_LEFT;
 			default: begin end
 		endcase
-		if(ucode_data[34:34]==0)
+		if(ucode_data[34:34]==0) /* Set reg read port 1 address */
 			reg_read_port1_addr=ucode_data[26:23];
 		IN_MOD=ucode_data[29:27];
-		if(ucode_data[35:35]==0)
+		if(ucode_data[35:35]==0) /* Set reg read port 1 address */
 			reg_read_port2_addr=ucode_data[33:30];
-		if(ucode_data[38:38]==1)
+		if(ucode_data[37:37]==1) /* Overwrite Wbit */
-			Wbit=ucode_data[37:37];
+			Wbit=ucode_data[38:38];
 		memio_address_select=ucode_data[39:39];
 		MEM_OR_IO=0;
 	end

system/general.v

@@ -22,8 +22,10 @@ input [1:0] sel;
 parameter WIDTH=16;
 input [WIDTH-1:0] in1,in2,in3,in4;
 output [WIDTH-1:0] out;
+
 assign out = (sel == 'b00) ? in1 :
 	(sel == 'b01) ? in2 :
 	(sel == 'b10) ? in3 :
 	in4;
+
 endmodule

system/memory.v

@@ -17,7 +17,7 @@
    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
-// don't ask for the full 1MiB especially since we don't even have segmentation
+/* This warning is because we don't use the full address bus. */
 /* verilator lint_off UNUSEDSIGNAL */
 module doublemem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,input BHE,input cs);
 /* verilator lint_on UNUSEDSIGNAL */

system/proc_state_def.v

@@ -51,7 +51,6 @@
 
 /*MEM/IO WRITE*/
 `define PROC_MEMIO_WRITE			6'b101000
-//`define PROC_MEMIO_WRITE_SETADDR		6'b010101
 `define PROC_MEMIO_PUT_ALIGNED_16BIT_DATA	6'b101001
 `define PROC_MEMIO_PUT_UNALIGNED_16BIT_DATA	6'b101010
 `define PROC_MEMIO_PUT_BYTE			6'b101011

system/processor.v

@@ -134,13 +134,6 @@ register_file register_file(
 
 reg [15:0] ProgCount;
 
-// verilator lint_off UNUSEDSIGNAL
-wire [15:0] ProgCount_next_opcode;
-wire [15:0] ProgCount_arg;
-assign ProgCount_next_opcode=ProgCount+{13'b0,instruction_size};
-assign ProgCount_arg=ProgCount+{15'b0,opcode_size}+16'd1;
-// verilator lint_on UNUSEDSIGNAL
-
 /*############ ALU / Execution units ########################################################## */
 //  ALU 1
 reg [1:0] in_alu1_sel1;

system/system.v

@@ -36,9 +36,6 @@ end
 always @(negedge wr) begin
 	if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )
 		$write("%s" ,data_bus[15:8]);
-	//if(CIR[7:0]==8'h21 && register_file.registers[0][15:8]==8'h02)begin
-	//	$write("%s" ,register_file.registers[2][7:0]);
-	//end
 end
 
 reg [1:0] finish;

system/testbench.cpp

@@ -17,9 +17,6 @@ void tick() {
 	system_state->clock = 0;
 	contextp->timeInc(timeinc);
 	system_state->eval();
-	//printf("tick() %04x\n",system_state->address_bus);
-	//trace->dump(timestamp);
-	//timestamp += 500/MHz;
 }
 
 int main(int argc, char** argv) {

system/ucode.txt

@@ -19,6 +19,7 @@
 
 //mas: MemIo Address Select
 //        0: register file output  1: alu output
+//
 //wbo: Wbit overwrite, {VALUE,ENABLE}. ex 11 would force one, 10 wouldn't do anything
 //
 //krs: Keep registers, selects weather the register port 1 and/or 2