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Removed redundant checks for enabled early instruction detection in BIU

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(Tim) Efthimis Kritikos 2023-10-23 02:26:06 +01:00
parent ced03c48d6
commit d151435ac1
1 changed files with 5 additions and 6 deletions
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11
system/biu.v
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@ -163,15 +163,14 @@ always @(posedge clock) begin
manner it seems that the assign statement updating FIFO_SIZE manner it seems that the assign statement updating FIFO_SIZE
doesn't work. PLEASE CLEAN UP THIS MESS */ doesn't work. PLEASE CLEAN UP THIS MESS */
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
/*TODO: do we need the last of the three parts ?*/ end else if((Isit1==1) && (FIFO_SIZE!=0))begin
end else if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
VALID_INSTRUCTION <= 1; VALID_INSTRUCTION <= 1;
INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
end else if((fifoIsize==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1) && `EARLY_VALID_INSTRUCTION_)begin end else if((fifoIsize==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1))begin
VALID_INSTRUCTION <= 1; VALID_INSTRUCTION <= 1;
INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1]; INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
end else if((fifoIsize==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2) && `EARLY_VALID_INSTRUCTION_)begin end else if((fifoIsize==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2))begin
VALID_INSTRUCTION <= 1; VALID_INSTRUCTION <= 1;
INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1]; INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
@ -365,11 +364,11 @@ always @( valid_instruction_ack ) begin
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize}; INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
`ifdef DOUBLE_INSTRUCTION_LOAD `ifdef DOUBLE_INSTRUCTION_LOAD
if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin
if((fifoIsize2==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}) && `EARLY_VALID_INSTRUCTION_)begin if((fifoIsize2==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}))begin
VALID_INSTRUCTION <= 1; VALID_INSTRUCTION <= 1;
INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1]; INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
end else if((fifoIsize2==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}) && `EARLY_VALID_INSTRUCTION_)begin end else if((fifoIsize2==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}))begin
VALID_INSTRUCTION <= 1; VALID_INSTRUCTION <= 1;
INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1]; INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];