More small fixes
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@ -47,10 +47,10 @@ always @ ( * ) begin
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`ALU_OP_ADD_SIGNED_B: {C_FLAG,OUT[7:0]}=A[7:0]+SIGNED_8B;
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`ALU_OP_ADD_SIGNED_B: {C_FLAG,OUT[7:0]}=A[7:0]+SIGNED_8B;
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`ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0];
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`ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0];
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`ALU_OP_SUB_REVERSE: {C_FLAG,OUT[7:0]}=B[7:0]-A[7:0];
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`ALU_OP_SUB_REVERSE: {C_FLAG,OUT[7:0]}=B[7:0]-A[7:0];
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`ALU_OP_AND: begin C_FLAG=0;OUT=A&B; end
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`ALU_OP_AND: begin C_FLAG=0;OUT[7:0]=A[7:0]&B[7:0]; end
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`ALU_OP_OR: begin C_FLAG=0;OUT=A|B; end
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`ALU_OP_OR: begin C_FLAG=0;OUT[7:0]=A[7:0]|B[7:0]; end
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`ALU_OP_XOR: begin C_FLAG=0;OUT=A^B; end
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`ALU_OP_XOR: begin C_FLAG=0;OUT[7:0]=A[7:0]^B[7:0]; end
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`ALU_OP_SHIFT_LEFT: begin C_FLAG=(A&16'h80)==16'h80;OUT=A<<B; end
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`ALU_OP_SHIFT_LEFT: begin C_FLAG=(A&16'h80)==16'h80;OUT[7:0]=A[7:0]<<B; end
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endcase
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endcase
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end
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end
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end
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end
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@ -117,25 +117,24 @@ always @(new_instruction) begin
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end
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end
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`endif
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`endif
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reg [1:0] finish;
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`ifndef YOSYS
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`ifndef SYNTHESIS
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string memdump_name;
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`endif
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always @(posedge HALT) begin
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`ifndef YOSYS
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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`endif
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finish<=2'd1;
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end
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`ifdef OTUPUT_JSON_STATISTICS
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`ifdef OTUPUT_JSON_STATISTICS
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reg [128:0] instruction_count_temp;
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reg [128:0] instruction_count_temp;
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`endif
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`endif
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`ifndef SYNTHESIS
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string memdump_name;
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always @(posedge HALT) begin
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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reg [1:0] finish;
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reg sane;
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reg sane;
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reg [128:0] cycles;
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reg [128:0] cycles;
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