Removed erroneous file and run aspell

This commit is contained in:
(Tim) Efthimis Kritikos 2023-03-21 14:51:39 +00:00
parent c25d2eaf19
commit bd7610879f
4 changed files with 9 additions and 9 deletions

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out

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@ -588,10 +588,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
11'b1100_1101_???:begin
/* INT - execute interrupt handler */
/* 1 1 0 0 1 1 0 1 | DATA |*/
// [skiped] 1) push flags
// [skiped] 2) clear trap and interrupt enable flag
// [skiped] 3) push CS
// [skiped] 4) fetch CS from interrupt table
// [skipped] 1) push flags
// [skipped] 2) clear trap and interrupt enable flag
// [skipped] 3) push CS
// [skipped] 4) fetch CS from interrupt table
// 5) push ProgCount
// 6) fetch ProgCount from interrupt table
instruction_size=2;
@ -621,7 +621,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
11'b1100_1111_???:begin
/* IRET - Return from interrupt */
/* | 1 1 0 0 1 1 1 1 | */
// Sicne we only push one thing on the stack
// Since we only push one thing on the stack
// on INT we can just reuse the code from RET
instruction_size=1;
opcode_size=0;

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@ -62,7 +62,7 @@ always @(negedge write_port1_we) begin
end
end
`ifdef DEBUG_REG_WRITES
// Icarus verilog really doesn't like non-blocking assignments
// Icarus Verilog really doesn't like non-blocking assignments
// here
/* verilator lint_off BLKSEQ */
if(write_port1_addr[3:2]==2'b11)begin

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@ -1,4 +1,4 @@
# This file is basicly to make verilator compilation look pretty.
# This file is basically to make verilator compilation look pretty.
# If the project doesn't compile it might be because verilator handles compilation
# differently and this patch doesn't work anymore. In such case remove everything
# except the include Vsystem.mk line and try again.