Improved state logic

cpu/gtkwave_savefile.gtkw

@@ -1,25 +1,26 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Wed Feb  8 09:14:55 2023
+[*] Wed Feb  8 09:34:17 2023
 [*]
 [dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
-[dumpfile_mtime] "Wed Feb  8 09:14:04 2023"
-[dumpfile_size] 334
+[dumpfile_mtime] "Wed Feb  8 09:33:52 2023"
+[dumpfile_size] 362
 [savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
 [timestart] 0
 [size] 1630 1059
 [pos] -1 -1
-*-20.669413 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-20.795050 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [sst_width] 221
-[signals_width] 110
+[signals_width] 214
 [sst_expanded] 1
 [sst_vpaned_height] 313
 @28
 tb.p.clock[0]
 tb.p.reset[0]
 tb.p.start[0]
-@29
 tb.p.state[1:0]
+@29
+tb.p.instruction_finished[0]
 [pattern_trace] 1
 [pattern_trace] 0

cpu/processor.v

@@ -6,7 +6,7 @@ module clock_gen (input enable, output reg clk);
   parameter PHASE = 0;    // in degrees
   parameter DUTY = 50;    // in percentage 
   
-  real clk_pd  		= 1.0/FREQ * 1000000; 	// convert to ns
+  real clk_pd  		= 1.0/FREQ * 1000000; 	// convert to ms
   real clk_on  		= DUTY/100.0 * clk_pd;
   real clk_off 		= (100.0 - DUTY)/100.0 * clk_pd;
   real quarter 		= clk_pd/4;
@@ -55,26 +55,36 @@ endmodule
 module processor ( input clock, input reset );
   reg [1:0] state;
   reg start=0;
+  reg instruction_finished;
 
+  /* RESET LOGIC */
   always @(negedge reset) begin
     if (reset==0) begin
       @(posedge clock);
       state=0;
       #10
       start=1;
-      //while (reset==0) begin
-      //end
-      //while (clock==0) begin
-      //end// skip this half-way through clock cycle
-      //start=1;
     end
   end
 
+  /* CLOCK LOGIC */
   always @(posedge clock) begin
+    if(instruction_finished) begin 
+      state =0;
+    end else begin
       if (clock && start==1) begin
         state=state+1;
       end
     end
+  end
+
+  always @(state) begin
+	  if (state==2) begin
+		  instruction_finished=1;
+	  end else begin
+		  instruction_finished=0;
+	  end
+  end
 
 
 endmodule