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Removed more "conflicting driver" issues with yet more performance penalties...

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-04 15:33:23 +00:00
parent df2975fa09
commit aa9b7c0a50
4 changed files with 182 additions and 179 deletions
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BIN
boot_code/brainfuck_mandelbrot.fst.hier
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16
system/decoder.v
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@ -104,6 +104,7 @@ reg owe_set_init;
reg VALID_INSTRUCTION_lc; reg VALID_INSTRUCTION_lc;
always @(VALID_INSTRUCTION)begin VALID_INSTRUCTION_lc<=VALID_INSTRUCTION; end always @(VALID_INSTRUCTION)begin VALID_INSTRUCTION_lc<=VALID_INSTRUCTION; end
reg wait_;
always @(posedge clock)begin always @(posedge clock)begin
if(reset==0)begin if(reset==0)begin
@ -119,8 +120,11 @@ always @(posedge clock)begin
HALT_LATCHED <= 0; HALT_LATCHED <= 0;
ERROR_LATCHED <= `ERROR_BITS'h0; ERROR_LATCHED <= `ERROR_BITS'h0;
VALID_INSTRUCTION_ACK <= 0; VALID_INSTRUCTION_ACK <= 0;
wait_<=0;
end else begin end else begin
if(next_exec==1'b1)begin if(wait_!=0)
wait_<=0;
else if(next_exec==1'b1)begin
if ( ( VALID_INSTRUCTION_lc == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin if ( ( VALID_INSTRUCTION_lc == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin
//`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work? //`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work?
IN_MOD_LATCHED <= IN_MOD; IN_MOD_LATCHED <= IN_MOD;
@ -147,6 +151,7 @@ always @(posedge clock)begin
SIMPLE_MICRO <= 1; SIMPLE_MICRO <= 1;
first_ucode <= 1; first_ucode <= 1;
set_initial_values <= !set_initial_values; set_initial_values <= !set_initial_values;
valid_exec_data<=0;
end else begin end else begin
if(SIMPLE_MICRO==0||first_ucode==1||owe_set_init==1)begin if(SIMPLE_MICRO==0||first_ucode==1||owe_set_init==1)begin
first_ucode <= 0; first_ucode <= 0;
@ -165,7 +170,8 @@ always @(posedge clock)begin
set_initial_values <= !set_initial_values; set_initial_values <= !set_initial_values;
end end
/* This runs at the start of each execution cycle, with microcode this is more than once per 8086 instruction */ /* This runs at the start of each execution cycle, with microcode this is more than once per 8086 instruction */
valid_exec_data<=!valid_exec_data; valid_exec_data<=1;
wait_<=1;
if( SIMPLE_MICRO == 1 ) begin if( SIMPLE_MICRO == 1 ) begin
ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/ ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
@ -174,8 +180,10 @@ always @(posedge clock)begin
end end
end end
end end
end end else
end valid_exec_data<=0;
end else
valid_exec_data<=0;
end end
end end

1
system/exec_state_def.v
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@ -21,6 +21,7 @@
`define EXEC_STATE_BITS 4 `define EXEC_STATE_BITS 4
//TODO: Please clean this up
`define EXEC_WAIT 4'b1100 `define EXEC_WAIT 4'b1100
/*DECODE SATE*/ /*DECODE SATE*/

344
system/execute.v
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@ -93,143 +93,54 @@ ALU ALU1(
/*############ Execute logic ########################################################## */ /*############ Execute logic ########################################################## */
always @(valid_input) begin
exec_state <= init_state;
reg_write_we <= 1;
biu_jump_req <= 0;
use_exec_reg_addr <= 0;
next_exec<=0;
end
always @( set_initial_values) begin always @( set_initial_values) begin
PARAM1 <= PARAM1_INIT; PARAM1 <= PARAM1_INIT;
PARAM2 <= PARAM2_INIT; PARAM2 <= PARAM2_INIT;
end end
always @(negedge reset) begin
exec_state <= `EXEC_WAIT;
end
always @(posedge reset) begin
exec_state <= `EXEC_RESET;
end
`define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE; `define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
`define finished_instruction exec_state <= `EXEC_WAIT;next_exec<=1; `define finished_instruction exec_state <= `EXEC_WAIT;next_exec<=1;
always @(posedge clock) begin always @(posedge clock) begin
case (exec_state) if ( !reset ) begin
`EXEC_RESET: begin exec_state <= `EXEC_RESET;
biu_write_request <= 0; end else begin
biu_read_request <= 0; case (exec_state)
biu_jump_req <= 0; `EXEC_RESET: begin
reg_write_we <= 1; biu_write_request <= 0;
exec_state <= `EXEC_WAIT;
ERROR <= `ERR_NO_ERROR;
end
`EXEC_WAIT:begin
reg_write_we <= 1;
use_exec_reg_addr <= 0;
ERROR<=`ERR_NO_ERROR;
next_exec<=1;
end
`EXEC_DE_LOAD_REG_TO_PARAM:begin
PARAM2<=reg_read_port2_data;
case(IN_MOD)
3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
default: exec_state <= `EXEC_WRITE_ENTRY;
endcase
end
`EXEC_MEMIO_READ:begin
/*Decode MOD R/M, read the data and place it to PARAM1*/
case (IN_MOD)
3'b000,
3'b001,
3'b010:begin
case (RM)
3'b000:begin
/*[BX]+[SI]*/
`unimpl_addressing_mode
end
3'b001:begin
/*[BX]+[SI]*/
`unimpl_addressing_mode
end
3'b010:begin
/*[BP]+[SI]*/
`unimpl_addressing_mode
end
3'b011:begin
/*[BP]+[DI]*/
`unimpl_addressing_mode
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr <= 4'b1110;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_READ_SETADDR;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr <= 4'b1111;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_READ_SETADDR;
end
3'b110:begin
/*d16 */
`unimpl_addressing_mode
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr <= 4'b1011;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_READ_SETADDR;
end
endcase
if(IN_MOD!=3'b000)begin
/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
`unimpl_addressing_mode;
end
end
3'b110:begin /* SP Indirect read*/
reg_read_port1_addr <= 4'b1100;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_READ_SETADDR;
end
default:begin
`unimpl_addressing_mode
end
endcase
end
`EXEC_MEMIO_READ_SETADDR:begin
if(memio_address_select==0)
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
else
BIU_ADDRESS_INPUT <= ALU_O;
if ( BIU_VALID_DATA == 1 ) begin
exec_state <= `EXEC_WRITE_ENTRY;
PARAM2 <= BIU_EX_DATA_READ;
biu_read_request <= 0; biu_read_request <= 0;
end else begin biu_jump_req <= 0;
biu_read_request <= 1; reg_write_we <= 1;
exec_state <= `EXEC_WAIT;
ERROR <= `ERR_NO_ERROR;
end end
end `EXEC_WAIT:begin
`EXEC_NEXT_INSTRUCTION:begin if(valid_input)begin
`finished_instruction exec_state <= init_state;
/*necessary for biu to see we went on another state from decode to give us a new instruction*/ next_exec<=0;
end end else begin
`EXEC_WRITE_ENTRY:begin next_exec<=1;
EX2DE_FLAGS[7:0] <= ALU_FLAGS[7:0]; end
case(OUT_MOD) biu_jump_req <= 0;
3'b000, reg_write_we <= 1;
3'b001, use_exec_reg_addr <= 0;
3'b010 : begin ERROR<=`ERR_NO_ERROR;
if(memio_address_select==1) end
exec_state <= `EXEC_MEMIO_WRITE; `EXEC_DE_LOAD_REG_TO_PARAM:begin
else PARAM2<=reg_read_port2_data;
case (RM) /* Duplicate code with write... */ case(IN_MOD)
3'b000,3'b001,3'b010: exec_state <= `EXEC_MEMIO_READ;
default: exec_state <= `EXEC_WRITE_ENTRY;
endcase
end
`EXEC_MEMIO_READ:begin
/*Decode MOD R/M, read the data and place it to PARAM1*/
case (IN_MOD)
3'b000,
3'b001,
3'b010:begin
case (RM)
3'b000:begin 3'b000:begin
/*[BX]+[SI]*/ /*[BX]+[SI]*/
`unimpl_addressing_mode `unimpl_addressing_mode
@ -250,13 +161,13 @@ always @(posedge clock) begin
/*[SI]*/ /*[SI]*/
reg_read_port1_addr <= 4'b1110; reg_read_port1_addr <= 4'b1110;
use_exec_reg_addr <= 1; use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE; exec_state <= `EXEC_MEMIO_READ_SETADDR;
end end
3'b101:begin 3'b101:begin
/*[DI]*/ /*[DI]*/
reg_read_port1_addr <= 4'b1111; reg_read_port1_addr <= 4'b1111;
use_exec_reg_addr <= 1; use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE; exec_state <= `EXEC_MEMIO_READ_SETADDR;
end end
3'b110:begin 3'b110:begin
/*d16 */ /*d16 */
@ -266,60 +177,143 @@ always @(posedge clock) begin
/*[BX]*/ /*[BX]*/
reg_read_port1_addr <= 4'b1011; reg_read_port1_addr <= 4'b1011;
use_exec_reg_addr <= 1; use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE; exec_state <= `EXEC_MEMIO_READ_SETADDR;
end end
endcase endcase
end if(IN_MOD!=3'b000)begin
3'b011:begin /*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
reg_write_we <= 0; `unimpl_addressing_mode;
`finished_instruction end
end end
3'b100:begin /*No output*/ 3'b110:begin /* SP Indirect read*/
`finished_instruction reg_read_port1_addr <= 4'b1100;
end use_exec_reg_addr <= 1;
3'b101:begin /* Program Counter*/ exec_state <= `EXEC_MEMIO_READ_SETADDR;
BIU_ADDRESS_INPUT <= ALU_O[15:0]; end
biu_jump_req <= 1; default:begin
exec_state <= `EXEC_JUMP_RELEASE; `unimpl_addressing_mode
end end
3'b110:begin /* SP Indirect write*/ endcase
reg_read_port1_addr <= 4'b1100; end
use_exec_reg_addr <= 1; `EXEC_MEMIO_READ_SETADDR:begin
exec_state <= `EXEC_MEMIO_WRITE; if(memio_address_select==0)
end BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
3'b111:begin /* Write to PRAM1 (for microcode calculations) */ else
PARAM1 <= ALU_O; BIU_ADDRESS_INPUT <= ALU_O;
`finished_instruction
end
default:begin
`unimpl_addressing_mode
end
endcase
end
`EXEC_JUMP_RELEASE:begin
biu_jump_req <= 0;
`finished_instruction
end
`EXEC_MEMIO_WRITE:begin
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
biu_write_request <= 1; if ( BIU_VALID_DATA == 1 ) begin
exec_state <= `EXEC_WRITE_ENTRY;
if(memio_address_select==0) PARAM2 <= BIU_EX_DATA_READ;
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0]; biu_read_request <= 0;
else end else begin
BIU_ADDRESS_INPUT <= ALU_O; biu_read_request <= 1;
end
if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow end
biu_write_request <= 0; `EXEC_NEXT_INSTRUCTION:begin
`finished_instruction
/*necessary for biu to see we went on another state from decode to give us a new instruction*/
end
`EXEC_WRITE_ENTRY:begin
EX2DE_FLAGS[7:0] <= ALU_FLAGS[7:0];
case(OUT_MOD)
3'b000,
3'b001,
3'b010 : begin
if(memio_address_select==1)
exec_state <= `EXEC_MEMIO_WRITE;
else
case (RM) /* Duplicate code with write... */
3'b000:begin
/*[BX]+[SI]*/
`unimpl_addressing_mode
end
3'b001:begin
/*[BX]+[SI]*/
`unimpl_addressing_mode
end
3'b010:begin
/*[BP]+[SI]*/
`unimpl_addressing_mode
end
3'b011:begin
/*[BP]+[DI]*/
`unimpl_addressing_mode
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr <= 4'b1110;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr <= 4'b1111;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE;
end
3'b110:begin
/*d16 */
`unimpl_addressing_mode
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr <= 4'b1011;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE;
end
endcase
end
3'b011:begin
reg_write_we <= 0;
`finished_instruction
end
3'b100:begin /*No output*/
`finished_instruction
end
3'b101:begin /* Program Counter*/
BIU_ADDRESS_INPUT <= ALU_O[15:0];
biu_jump_req <= 1;
exec_state <= `EXEC_JUMP_RELEASE;
end
3'b110:begin /* SP Indirect write*/
reg_read_port1_addr <= 4'b1100;
use_exec_reg_addr <= 1;
exec_state <= `EXEC_MEMIO_WRITE;
end
3'b111:begin /* Write to PRAM1 (for microcode calculations) */
PARAM1 <= ALU_O;
`finished_instruction
end
default:begin
`unimpl_addressing_mode
end
endcase
end
`EXEC_JUMP_RELEASE:begin
biu_jump_req <= 0;
`finished_instruction `finished_instruction
end end
`EXEC_MEMIO_WRITE:begin
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
end biu_write_request <= 1;
default:begin
end if(memio_address_select==0)
endcase BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
else
BIU_ADDRESS_INPUT <= ALU_O;
if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
biu_write_request <= 0;
`finished_instruction
end
end
default:begin
end
endcase
end
end end
endmodule endmodule