I2C_BOOTLOADER: Several fixes and a 4.5x performance increase as well as the addition of 16bit reads from the I2C_driver
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@ -19,74 +19,123 @@ outb #0x63
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mov al,#0x00
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outb #0x60
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;wait_send: inw #0x62
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;test al,#0x01
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;jnz wait_send
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mov ax,#0x1FFE
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aa:
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dec ax
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jnz aa
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wait_send: inb #0x62
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test al,#0x01
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jnz wait_send
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mov bx,#OK_loading_txt
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call print
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;############ READ 20% ##################
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;############ READ CODE ##################
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mov bx,#0xD000
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mov bx,#0xEFFF
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mov di,#0x0000
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rom_read_loop:
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mov al,#0x05 ; Read, 8bit, ignore ack
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mov al,#0x07 ; Read, 8bit, ignore ack
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outb #0x63
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mov al,#0x00
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outb #0x60
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mov ax,#0x1FFE
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aa2:
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dec ax
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jnz aa2
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push bx
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cmp di,#0x1800
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jz print_10
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cmp di,#0x3000
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jz print_20
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cmp di,#0x4800
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jz print_30
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cmp di,#0x6000
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jz print_40
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cmp di,#0x7800
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jz print_50
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cmp di,#0x9000
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jz print_60
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cmp di,#0xA800
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jz print_70
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cmp di,#0xC000
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jz print_80
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cmp di,#0xD800
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jz print_90
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back:
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pop bx
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wait_send2: inb #0x62
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test al,#0x01
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jnz wait_send2
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inw #0x60
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STOSB
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cmp di,#0x2999
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jz print_20
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cmp di,#0x5333
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jz print_40
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cmp di,#0x7CCC
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jz print_60
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cmp di,#0xA666
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jz print_80
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back:dec bx
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jnz rom_read_loop
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;MOV CL,AH
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;MOV AH,AL
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;MOV AL,CL
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STOSW
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dec bx
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jz rom_read_end
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dec bx
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jz rom_read_end
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jmp rom_read_loop
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rom_read_end:
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MOV AX,#0xC000
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JMP AX
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print_10:
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mov cx,#ten_prc_txt
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call print_prc
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jmp back
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print_20:
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mov bx,#twenty_prc_txt
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call print
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mov cx,#twenty_prc_txt
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call print_prc
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jmp back
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print_30:
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mov cx,#thirty_prc_txt
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call print_prc
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jmp back
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print_40:
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mov bx,#forty_prc_txt
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call print
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mov cx,#forty_prc_txt
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call print_prc
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jmp back
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print_50:
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mov cx,#fifty_prc_txt
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call print_prc
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jmp back
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print_60:
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mov bx,#sixty_prc_txt
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call print
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mov cx,#sixty_prc_txt
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call print_prc
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jmp back
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print_70:
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mov cx,#seventy_prc_txt
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call print_prc
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jmp back
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print_80:
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mov bx,#eighty_prc_txt
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call print
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mov cx,#eighty_prc_txt
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call print_prc
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jmp back
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print_90:
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mov cx,#ninty_prc_txt
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call print_prc
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jmp back
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print_prc:
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mov bx,#loading_rom_txt
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call print
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mov bx,cx
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call print
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ret
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;#########################################
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include LiteDram_init.asm
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@ -105,10 +154,16 @@ STACK: ; brainfuck_mandelbrot depends on stack being at the end
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load_i2c_txt: .ASCII 'Read I2C EEPROM:\0'
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OK_loading_txt: .ASCII 'OK\nLoading rom 0%\r\0'
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twenty_prc_txt: .ASCII 'Loading rom 20%\r\0'
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forty_prc_txt: .ASCII 'Loading rom 40%\r\0'
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sixty_prc_txt: .ASCII 'Loading rom 60%\r\0'
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eighty_prc_txt: .ASCII 'Loading rom 80%\r\0'
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loading_rom_txt: .ASCII 'Loading rom \0'
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ten_prc_txt: .ASCII '10%\r\0'
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twenty_prc_txt: .ASCII '20%\r\0'
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thirty_prc_txt: .ASCII '30%\r\0'
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forty_prc_txt: .ASCII '40%\r\0'
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fifty_prc_txt: .ASCII '50%\r\0'
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sixty_prc_txt: .ASCII '60%\r\0'
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seventy_prc_txt: .ASCII '70%\r\0'
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eighty_prc_txt: .ASCII '80%\r\0'
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ninty_prc_txt: .ASCII '90%\r\0'
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.ORG 0xFFF0
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MOV AX,#0xF800
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@ -38,7 +38,7 @@ module I2C_driver (
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reg DIR_latched;
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reg SDA;
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reg SDA; // TODO make SDA_output a reg and rename everything
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assign SDA_output=SDA;
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@ -181,8 +181,6 @@ always @(posedge clock) begin
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6'b010110:begin
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SCL<=1;
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if(DIR_latched==1'b1)begin
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//i2c_data_read[15:0]<={8'h0,SDA_input,i2c_data_read[7:1]};
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i2c_data_read[15:0]<={8'h0,i2c_data_read[6:0],SDA_input};
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end
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i2c_state<=6'b010111;
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@ -197,12 +195,21 @@ always @(posedge clock) begin
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end
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/****** Acknowledge ********/
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6'b011000:begin
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// Note: If we read we want to send an ack,
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// If we write we want to read an ack so it's reversed here
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if(DIR_latched==1'b1)begin
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SDA_direction<=1;
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end else begin
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SDA_direction<=0;
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end
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SCL<=0;
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i2c_state<=6'b011001;
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end
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6'b011001:begin
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SCL<=0;
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if(DIR_latched==1'b1)begin
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SDA<=1'b0;
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end
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i2c_state<=6'b011010;
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end
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6'b011010:begin
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@ -211,13 +218,12 @@ always @(posedge clock) begin
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end
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6'b011011:begin
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SCL<=1;
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if (SDA_input==0||ignore_ack==1'b1)begin
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if (SDA_input==0||DIR_latched==1'b1)begin
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if(trans_width_latch==1'b1)begin
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i2c_state<=6'b100101;
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data_bit_counter<=4'd0;
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end else
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i2c_state<=6'b011100;
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SDA_direction<=1;
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end else begin
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i2c_state<=6'b111111;
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end
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@ -225,18 +231,27 @@ always @(posedge clock) begin
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/****** Send data (16bit) ********/
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6'b100101:begin
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SCL<=0;
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if(DIR_latched==1'b1)begin
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SDA_direction<=0;
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end else begin
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SDA_direction<=1;
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end
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i2c_state<=6'b100110;
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end
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6'b100110:begin
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SCL<=0;
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if(DIR_latched==1'b0)begin
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SDA<=data_internal[15:15];
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data_internal[15:8]<={data_internal[14:8],1'b0};
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end
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b100111;
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end
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6'b100111:begin
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SCL<=1;
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if(DIR_latched==1'b1)begin
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i2c_data_read[15:0]<={i2c_data_read[14:8],SDA_input,i2c_data_read[7:0]};
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end
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i2c_state<=6'b101000;
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end
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6'b101000:begin
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