Service Pack 1: Added some needed instructions for what will probably be some of the V0.2.0 test programs
This commit is contained in:
parent
98e73af5da
commit
900610426d
2
Makefile
2
Makefile
@ -21,7 +21,7 @@ VERILATOR_BIN=system/obj_dir/Vsystem
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BOOT_CODE=boot_code/brainfuck_mandelbrot.txt
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GTKWSAVE=./gtkwave_savefile.gtkw
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MICROCODE=system/ucode.txt
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BOOTABLES=boot_code/brainfuck_compiled.txt boot_code/brainfuck_interpreted.txt ${BOOT_CODE}
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BOOTABLES=boot_code/brainfuck_compiled.txt boot_code/brainfuck_interpreted.txt ${BOOT_CODE} boot_code/fibonacci.txt boot_code/gnome_sort.txt
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NO_ASM=1
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include common.mk
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@ -1,9 +1,10 @@
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SOURCE=brainfuck_interpreted.asm brainfuck_compiled.asm brainfuck_mandelbrot.asm
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SOURCE=brainfuck_interpreted.asm brainfuck_compiled.asm brainfuck_mandelbrot.asm fibonacci.asm gnome_sort.asm
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BINARIES=$(subst .asm,.txt,${SOURCE})
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BUILD_FILES=${BINARIES}
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BUILD_FILES+=$(subst .asm,.memdump,${SOURCE})
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BUILD_FILES+=$(subst .asm,.fst,${SOURCE})
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BUILD_FILES+=$(subst .asm,.bin,${SOURCE})
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BUILD_FILES+=$(subst .asm,.json,${SOURCE})
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all: ${BINARIES}
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@ -11,6 +12,9 @@ brainfuck_interpreted.bin: brainfuck_interpreter_v0.asm hello_9086.bf.asm dos_la
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brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
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brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm
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fibonacci.bin: helpers.asm
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gnome_sort.bin: helpers.asm
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%.bf.asm:%.bf
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${Q}sed "s/[a-zA-Z\* ]//g;/^$$/d;s/^/.ASCII '/;s/\$$/'/" "$^" > $@
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38
boot_code/fibonacci.asm
Normal file
38
boot_code/fibonacci.asm
Normal file
@ -0,0 +1,38 @@
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INCLUDE dos_layer.asm
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org 0x100
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mov sp,#STACK
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MOV AX,#0x1
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MOV BX,#0x1
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CALL PRINT_16_HEX
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push bx
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MAIN_LOOP:
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pop bx
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CALL PRINT_16_HEX
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push AX
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ADD AX,BX
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JNC MAIN_LOOP
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pop bx
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MOV AH,#0x02
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MOV DL,#0x0a
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INT #0x21
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hlt
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.BLKB 200
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STACK:
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INCLUDE helpers.asm
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.ORG 0xFFF0
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MOV AX,#0x0100
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JMP AX
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54
boot_code/gnome_sort.asm
Normal file
54
boot_code/gnome_sort.asm
Normal file
@ -0,0 +1,54 @@
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INCLUDE dos_layer.asm
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.org 0x100
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mov sp,#STACK
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MOV SI,#DATA
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GNOME_SORT:
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CMP SI,#DATA+31
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JZ GNOMED
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MOV AX,[SI]
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INC SI
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CMP AH,AL
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JAE GNOME_SORT
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SWAP:
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MOV BL,AL
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MOV AL,AH
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MOV AH,BL
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DEC SI
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MOV [SI],AX
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CMP SI,#DATA
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JZ GNOME_SORT
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DEC SI
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JMP GNOME_SORT
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GNOMED:
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MOV SI,#DATA
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PRINT_LOOP:
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MOV AL,[SI]
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call PRINT_0_8_HEX
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INC SI
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CMP SI,#DATA+32
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JNZ PRINT_LOOP
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MOV AH,#0x02
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MOV DL,#0x0a
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INT #0x21
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hlt
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DATA: DB 0x51, 0x17, 0x37, 0x5d, 0x06, 0x3f, 0x51, 0x8b
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DB 0xa5, 0x33, 0x54, 0xdf, 0xae, 0xee, 0x3a, 0x18
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DB 0xe9, 0xdb, 0x1f, 0x21, 0x44, 0x4f, 0x99, 0x09
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DB 0x2a, 0x23, 0x82, 0x4f, 0x52, 0xf1, 0xdc, 0x0b
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.BLKB 200
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STACK:
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INCLUDE helpers.asm
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.ORG 0xFFF0
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MOV AX,#0x0100
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JMP AX
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93
boot_code/helpers.asm
Normal file
93
boot_code/helpers.asm
Normal file
@ -0,0 +1,93 @@
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;Input AX
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PRINT_16_HEX:
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PUSH DX
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TEST AH,#0xF0
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jz NOT_FIRST_NIBBLE
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MOV DL,AH
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CALL PRINT_HIGH
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JMP SKIP1
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NOT_FIRST_NIBBLE:
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TEST AH,#0x0F
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jz NOT_SECOND_NIBBLE
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SKIP1:
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MOV DL,AH
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CALL PRINT_LOW
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JMP SKIP2
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NOT_SECOND_NIBBLE:
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TEST AL,#0xF0
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jz NOT_THIRD_NIBBLE
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SKIP2:
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MOV DL,AL
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CALL PRINT_HIGH
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NOT_THIRD_NIBBLE:
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MOV DL,AL
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CALL PRINT_LOW
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PUSH AX
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MOV AH,#0x02
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MOV DL,#0x20
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INT #0x21
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POP AX
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POP DX
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RET
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PRINT_HIGH:
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AND DL,#0xF0
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TEST DL,#0x80
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jz NOT1
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OR DL,#0x08
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NOT1:
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TEST DL,#0x40
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jz NOT2
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OR DL,#0x04
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NOT2:
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TEST DL,#0x20
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jz NOT3
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OR DL,#0x02
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NOT3:
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TEST DL,#0x10
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jz DONE
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OR DL,#0x01
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DONE:
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PRINT_LOW:
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PUSH AX
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AND DL,#0x0F
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CMP DL,#0x0A
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JNS LETTERS
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ADD DL,#0x30
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MOV AH,#0x02
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INT #0x21
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POP AX
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RET
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LETTERS:
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ADD DL,#0x37
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MOV AH,#0x02
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INT #0x21
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POP AX
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RET
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PRINT_0_8_HEX:
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MOV DL,AL
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PUSH AX
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CALL PRINT_HIGH
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POP AX
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MOV DL,AL
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CALL PRINT_LOW
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PUSH AX
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MOV AH,#0x02
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MOV DL,#0x20
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INT #0x21
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POP AX
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RET
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125
system/decoder.v
125
system/decoder.v
@ -184,19 +184,22 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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in_alu1_sel1=2'b00;
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OUT_MOD=3'b100;
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MEM_OR_IO=0;
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ALU_1OP=`ALU_OP_SUB;
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ALU_1OP=`ALU_OP_SUB_REVERSE;
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memio_address_select=0;
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if(IN_MOD==3'b011)begin
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/*compare register with param*/
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in_alu1_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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next_state=`PROC_DE_LOAD_8_PARAM;
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end else begin
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/*compare register indirect access
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* with param */
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in_alu1_sel2=2'b00;
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next_state=`PROC_DE_LOAD_16_PARAM; /*will then call MEMIO_READ*/
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/*will call MEMIO_READ after EXEC_DE_LOAD..*/
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end
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if (Wbit)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else
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next_state=`PROC_DE_LOAD_8_PARAM;
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`normal_instruction;
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end
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11'b1011_0???_??? : begin
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@ -364,7 +367,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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in_alu1_sel2=2'b01;
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reg_read_port2_addr={Wbit,3'b000};
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OUT_MOD=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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ALU_1OP=`ALU_OP_SUB_REVERSE;
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MEM_OR_IO=0;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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@ -423,6 +426,13 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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else
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next_state=`PROC_EX_STATE_ENTRY;
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end
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3'b001: begin
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/* Jump on (not) Carry */
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if(FLAGS[0:0]==CIR[8:8])
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next_state=`PROC_IF_STATE_ENTRY;
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else
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next_state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction; /*We don't support that condition*/
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end
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@ -526,6 +536,29 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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`normal_instruction;
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memio_address_select=0;
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end
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11'b1010_100?_???:begin
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/* TEST - Bitwise AND of immediate and accumulator affecting only flags */
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/* 1 0 1 0 1 0 0 W | DATA | DATA if W | */
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opcode_size=0;
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Wbit=CIR[8:8];
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IN_MOD=3'b011;
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RM=3'b000;
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MEM_OR_IO=0;
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if(Wbit==1)begin
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instruction_size=3;
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next_state=`PROC_DE_LOAD_16_PARAM;
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end else begin
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instruction_size=2;
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next_state=`PROC_DE_LOAD_8_PARAM;
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end
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in_alu1_sel1=2'b00; /* PARAM1 */
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ALU_1OP=`ALU_OP_AND;
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in_alu1_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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OUT_MOD=3'b100;/*NULL*/
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`normal_instruction;
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memio_address_select=0;
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end
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11'b0101_1???_???:begin
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/* POP - REG=[SP]; SP+=2 */
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/* | 0 1 0 1 1 REG | */
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@ -629,6 +662,90 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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seq_addr_entry<=`UCODE_RET_ENTRY;
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memio_address_select=0;
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end
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11'b1000_000?_100,11'b1000_000?_001:begin
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/* OR - Bitwise OR immediate and register/mem */
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/* 1 0 0 0 0 0 0 W | MOD 0 0 1 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */
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/* AND - Bitwise AND immediate and register/mem */
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/* 1 0 0 0 0 0 0 W | MOD 1 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */
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opcode_size=1;
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Wbit=CIR[8:8];
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IN_MOD={1'b0,CIR[7:6]};
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RM={CIR[2:0]};
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MEM_OR_IO=0;
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if(Wbit==1)begin
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instruction_size=4;
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next_state=`PROC_DE_LOAD_16_PARAM;
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end else begin
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instruction_size=3;
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next_state=`PROC_DE_LOAD_8_PARAM;
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end
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in_alu1_sel1=2'b00; /* PARAM1 */
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case(CIR[5:3])
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3'b100: ALU_1OP=`ALU_OP_AND;
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3'b001: ALU_1OP=`ALU_OP_OR;
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default:begin end
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endcase
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case(IN_MOD)
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3'b011:begin
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in_alu1_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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`normal_instruction;
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end
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default:begin
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`invalid_instruction;
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end
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endcase
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OUT_MOD=IN_MOD;
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memio_address_select=0;
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end
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11'b0000_00??_???,11'b0010_10??_???,11'b0011_10??_???:begin
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/* CMP - Compare Register/memory and register */
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/* 0 0 1 1 1 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
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/* SUB - Reg/memory with register to either */
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/* 0 0 1 0 1 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
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/* ADD - Reg/memory with register to either */
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/* 0 0 0 0 0 0 D W | MOD REG R/M | < DISP LO > | < DISP HI > | */
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instruction_size=2;
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opcode_size=1;
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Wbit=CIR[8:8];
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Sbit=0;
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IN_MOD=3'b011;
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RM=CIR[2:0];
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in_alu1_sel1=2'b01;//constantly register
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reg_read_port1_addr={Wbit,CIR[5:3]};
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if(IN_MOD==3'b011)begin
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in_alu1_sel2=2'b01;
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reg_read_port2_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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next_state=`PROC_EX_STATE_ENTRY;
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end else begin
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in_alu1_sel2=2'b00;
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if(Wbit)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else
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next_state=`PROC_DE_LOAD_8_PARAM;
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end
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MEM_OR_IO=0;
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memio_address_select=0;
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case (CIR[13:10])
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4'b0000: ALU_1OP=`ALU_OP_ADD;
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4'b1010: ALU_1OP=`ALU_OP_SUB;
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4'b1110: ALU_1OP=`ALU_OP_SUB_REVERSE;
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default: begin end
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endcase
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case (CIR[13:10])
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4'b0000: OUT_MOD={1'b0,CIR[7:6]};
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4'b1010: OUT_MOD={1'b0,CIR[7:6]};
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4'b1110: OUT_MOD=3'b100; /* NULL */
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default: begin end
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endcase
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if(CIR[9:9]==1'b0) begin
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`normal_instruction;
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end else begin
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`invalid_instruction
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end
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end
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default:begin
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`invalid_instruction
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end
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